LV594A Search Results

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413E – APRIL 1998 – REVISED OCTOBER 2002 D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 3 2 1 20 19

Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413F – APRIL 1998 – REVISED AUGUST 2003 D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 3 2 1 20 19

Contextual Info: LV594A 8-Bit Shift Register with Output Register The LV594A is an 8−bit shift register designed for 2 V to 6.0 V VCC operation. The device contain an 8−bit serial−in, parallel−out shift register that feeds an 8−bit D−type storage register.

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

LV594A

Abstract: 74LV594 A115-A C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413G − APRIL 1998 − REVISED SEPTEMBER 2003 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD LV594A
Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413C – APRIL 1998 – REVISED MAY 2000 D D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 4 3 2 1 20 19

Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413C – APRIL 1998 – REVISED MAY 2000 D D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 4 3 2 1 20 19

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413H − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999 D D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG description

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413C – APRIL 1998 – REVISED MAY 2000 D D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 4 3 2 1 20 19

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413H − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

610110

Abstract: A115-A C101 SN54LV594A SN74LV594A
Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413D – APRIL 1998 – REVISED JANUARY 2001 D D D D description 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: LV594A, LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413D – APRIL 1998 – REVISED JANUARY 2001 D D D D description 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ LV594A . . . FK PACKAGE TOP VIEW QD QE

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: LV594A, LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 LV594A . . . J OR W PACKAGE LV594A . . . D, DB, NS, OR PW PACKAGE TOP VIEW D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V