LV165 Search Results

LV138

Abstract: LV245 LV273 Flip-Flops lv373 LV164 LV125 LV174
Contextual Info: Contents Page LV Gates/MSI/Octals ’LVOO ’LV02 ’LV04 ’LVU04 ’LV08 ’LV14 ’LV32 ’LV74 'LV125 ’LV138 ’LV164 'LV165 ’LV174 'LV240 'LV244 ’LV245 'LV273 'LV373 ’LV374 ’LV573 'LV574 6-2 Quadruple 2-Input Positive-NAND G a t e s . 6-3

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per

A115-A

Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

25x16v

Contextual Info: LV165, LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B - MARCH 1996 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process typical Vq l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per

LV165A

Abstract: SN54LV165A SN74LV165A
Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

lv165a

Contextual Info: LV165A, LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: LV165A, LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.

A115-A

Abstract: C101 SN74LV165A-EP SN74LV165AMPWREP
Contextual Info: LV165A-EP PARALLEL-LOAD 8-BIT SHIFT REGISTER www.ti.com SCLS694 – JANUARY 2006 FEATURES • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: LV165A, LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode

Contextual Info: LV165A, LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

SN54LV165

Abstract: SN74LV165
Contextual Info: LV165, LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B – MARCH 1995 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: LV165A-EP PARALLEL-LOAD 8-BIT SHIFT REGISTER www.ti.com SCLS694 – JANUARY 2006 FEATURES • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: LV165A, LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode

Contextual Info: LV165A-EP PARALLEL-LOAD 8-BIT SHIFT REGISTER www.ti.com SCLS694 – JANUARY 2006 FEATURES • • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

Contextual Info: LV165A, LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402H – APRIL 1998 – REVISED JANUARY 2003 LV165A . . . J OR W PACKAGE LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK

74HC165

Abstract: Toshiba hay 22 forsythe 16V8 74ALVC16244 74HC595 GAL16LV8D QS3257 QS3384 MOTHERBOARD ibm rev.1.5
Contextual Info: Pyxis Chipset Spec December 5, 1996 Rev X2.1 Authors: Reinhard Schumann , Schumann@eng.pko.dec.com Don Rice, Rice@eng.pko.dec.com Digital Equipment Corporation 1995, All Rights Reserved The specifications contained herein are confidential and proprietary. The information in this document is

Contextual Info: LV165, LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B – MARCH 1995 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)