LV164 Search Results

Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D LV164A . . . J OR W PACKAGE LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D LV164A . . . J OR W PACKAGE LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

LV164A

Abstract: A115-A C101 SN54LV164A SN74LV164A
Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF

Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403E – APRIL 1998 – REVISED JUNE 2003 1 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC QH QG QF QE CLR CLK B QA QB QC QD 14 B A NC VCC QH 1 2 13 QH 3 12 QG 11 QF 4 LV164A . . . FK PACKAGE TOP VIEW

Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D Latch-Up Performance Exceeds 250 mA Per D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

IN74LV164

Abstract: IN74LV164D IN74LV164N IZ74LV164 IN74HC
Contextual Info: TECHNICAL DATA LV164 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER The LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the IN74HC/HCT164. The LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered

SN54LV164A

Abstract: SN74LV164A A115-A C101 LV164
Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

LV138

Abstract: LV245 LV273 Flip-Flops lv373 LV164 LV125 LV174
Contextual Info: Contents Page LV Gates/MSI/Octals ’LVOO ’LV02 ’LV04 ’LVU04 ’LV08 ’LV14 ’LV32 ’LV74 'LV125 ’LV138 ’LV164 'LV165 ’LV174 'LV240 'LV244 ’LV245 'LV273 'LV373 ’LV374 ’LV573 'LV574 6-2 Quadruple 2-Input Positive-NAND G a t e s . 6-3

Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403C – APRIL 1998 – REVISED MAY 2000 D D D D D D description The ’LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation. LV164A . . . J OR W PACKAGE

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

SN54LV164A

Abstract: SN74LV164A
Contextual Info: LV164A, LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403B – APRIL 1998 – REVISED JUNE 1998 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: LV164, LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS _ SCLS191B - FEBRUARY 1993 - R EVISED APRIL 1996 • E P IC Enhanced-Performance Implanted CMOS • • • • • 2-(X LV164. j or w package . .^db.orpw package

SN54LV164

Contextual Info: LV164, LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS191B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: LV164A, LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE