F1017 Search Results

application of parity checker/generator

Abstract: PQO-10 F10170 F10570
Contextual Info: F1017Ö« F10570 11-INPUT PARITY CHECKER/GENERATOR D E S C R IP T IO N — T h e F 1 0 1 70 a n d F1 0 5 70 a re v e ry h ig h -s p e e d 1 1 -In p u t P a rity C h e c k ­ e r /G e n e ra to rs . It is u s e fu l f o r d a ta p ro c e s s in g , m e m o ry a n d d a ta tr a n s m is s io n a p p lic a ­

Contextual Info: F10176^ F10576^ HIGH SPEED HEX D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL D E S C R IP TIO N — The F10176 and F10576 contain six high-speed master/slave D type flip-flops which have a common Clock. Data is entered into the master when the Clock is LOW. Data transfer takes place on the positive-going clock transition. A change in the

F1057

Contextual Info: F10175 • F10575 QUINT LATCH DESCRIPTION — The F10175 and F10575 are high-speed low-power Quint Latches. They feature five D type latches with common Reset and a common 2-input Enable. Data is transferred on the negative edge of the enable and latched on the positive edge.

Contextual Info: F1017Ó7* F10570 11-INPUT PARITY CHECKER/GENERATOR D E S C R IP TIO N — The F10170 and F10570 are very high-speed 11-In p u t Parity C heck­ er/G ene rato rs. It is useful fo r data processing, m e m ory and data tra nsm ission a p p lic a ­ tio n s. T w o o u tp u ts are provided; PoO-8 is H IG H w hen the re is an odd n u m b e ro f H IG H

Contextual Info: / J F10179 • F10579 CARRY LOOKAHEAD GENERATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION — T h e F10179 and F10579 are h ig h -sp e e d c a rry g en erato rs intended LOGIC SYMBOL fo r use with the F10181 4-bit A L U . T y p ic a l a d d itio n tim e s fo r tw o 32-b it w o rd s is 30 ns

fairchild ECL

Contextual Info: F10172 • F10572 DUAL l-O F-4 DECODER/DEMULTIPLEXER SELECTED OUTPUTS HIGH D E S C R IP TIO N — The F10172 and F10572 co n ta in a pa ir of 1-of-4 D e c o d e r/M u ltip le x ­ ers w ith C om m on E nable E c and A ddress (Ao and A i ) inpu ts. In each d e co d e r the

Contextual Info: F10173 • F io sy a"7 QUAD MULTIPLEXER/LATCH D E S C R IP TIO N — The F10173 and F10573 are Quad 2-Channel Multiplexers with latches. They incorporate a common Enable and a common Data Select Input. The Select input determines which Data input is enabled. A H IG H input enables Data Inputs

lem la 50 p

Abstract: 3a02a
Contextual Info: F10172 • F10572 DUAL l-OF-4 DECODER/DEMULTIPLEXER SELECTED OUTPUTS HIGH D E S C R IP TIO N — The F10172 and F10572 c o n ta in a pa ir o f 1-of-4 D e c o d e r/M u ltip le x ­ ers w ith C om m on Enable E c and A ddress (Ao and A i) inpu ts. In each d e c o d e r the

F10170

Abstract: F10570
Contextual Info: F10170 • F10570 1 l-INPUT PARITY CHECKER/GENERATOR D E S C R IP T IO N — The F10170 and F10570 are very high -spe ed 11 -Inp ut P arity C h e ck­ e r/G e n e ra to rs. It is useful fo r data processing , m e m ory and data tra n sm issio n a p p lic a ­

F10574

Contextual Info: F10174 • F10574 DUAL MULTIPLEXER FIOK-VOLTAGE COMPENSATED ECL D E S C R IP TIO N — The F10174 and F10574 are high-speed Dual Channel Multiplexers LOGIC SYMBOL with output enable capability. The Select inputs determine one of four active Data inputs for each m ultiplexer. When the Enable input is HIGH, both outputs are forced

Contextual Info: F10171 • DUAL 1-0F-4 DECODER/DEMULTIPLEXER SELECTED OUTPUTS LOW D E S C R IP TIO N — The F10171 and F10571 co n ta in a pa ir o f 1-of-4 D e c o d e r/M u ltip le x ­ ers w ith C om m on E nable E c and A ddress (Ao and A i) inpu ts. In each d e co d e r the

F10175

Abstract: F10575
Contextual Info: F10175 • F10575 QUINT LATCH DESCRIPTION — The F10175 and F10575 are high-speed low-power Quint Latches. They feature five D type latches with common Reset and a common 2-input Enable. Data is transferred on the negative edge of the enable and latched on the positive edge.

demultiplexer 3 to 8 truth table

Abstract: demultiplexer truth table Truth table of 1 to 16 demultiplexer F10172 F10572 5 to 32 decoder
Contextual Info: F10172 • F10572 DUAL 1-0F-4 DECODER/DEMULTIPLEXER SELECTED OUTPUTS HIGH D E S C R IP TIO N — The F10172 and F10572 c o n ta in a p a ir of 1-of-4 D e c o d e r/M u ltip le x ­ ers w ith C om m on Enable E c and A ddress (Ao and A i ) inpu ts. In each d e co d e r the

3XG0

Contextual Info: F10179 • F10579 CARRY LOOKAHEAD GENERATOR F10K VOLTAGE C OMPENSATED ECL D E S C R IP T IO N — T h e F 1 0 1 79 and fo r use w ith the F 10181 4 -b it A L U . w h en using F10181 in the ripp le g e n e ra to r is used, th e ty p ic a l add F 10579 are h ig h -s p e e d c arry g e n e ra to rs in ten ded

Contextual Info: F10174^ F10574 DUAL MULTIPLEXER FIOK-VOLTAGE COM PENSATED ECL D E S C R I P T I O N — T h e F 1 0 1 7 4 a n d F 1 0 5 7 4 a re h ig h - s p e e d D u a l C h a n n e l M u ltip le x e r s w ith o u tp u t e n a b le c a p a b ilit y . T h e S e le c t in p u ts d e t e r m in e o n e o f f o u r a c tiv e D a ta

demultiplexer truth table

Abstract: Truth table of 1 to 16 demultiplexer F10171 F10571 k 786
Contextual Info: F10171 • F10571^ DUAL 1-0F-4 DECODER/DEMULTIPLEXER SELECTEO OUTPUTS LOW D E S C R IP T IO N — T h e F10171 a n d F10571 c o n ta in a p a ir o f 1 -o f-4 D e c o d e r /M u ltip le x ­ e rs w ith C o m m o n E n a b le E c a n d A d d re s s (Ao a n d A i) in p u ts . In e a c h d e c o d e r th e

circuit diagram of 16-1 multiplexer

Abstract: F10173 F10573 circuit of 16-1 multiplexer VCC164
Contextual Info: F 10173 * F10573 QUAD MULTIPLEXER/LATCH D E S C R IP T IO N — T h e F10173 and F1 0 5 73 a re Q u ad 2 -C h a n n e l M u ltip lex e rs w ith latches. T h e y in co rp o rate a c o m m o n E nable and a c o m m o n D a ta S e le c t In p u t. T h e S e le c t in put d e te rm in e s w h ich D a ta in put is e n a b le d . A H IG H in put enab le s D a ta inputs

F10179

Abstract: F10181 F10579 G2 - 395 P2S3
Contextual Info: F10179 • F10579 CARRY LOOKAHEAD GENERATOR F10K VOLTAGE COMPENSATED ECL D E SC R IP TIO N — The F10179 and for use with the F10181 4-bit ALU. when using F10181 in the ripple generator is used, the typical add F10579 are high-speed carry generators intended

F10174

Abstract: F10574
Contextual Info: F10174^ F10574 DUAL M ULTIPLEXER FIOK-VOLTAGE COMPENSATED ECL D E S C R IP T IO N — T h e F 1 0 1 7 4 a n d F10574 a re h ig h -s p e e d D u a l C h a n n e l M u ltip le x e r s w ith o u tp u t e n a b le c a p a b ility . T h e S e le c t in p u ts d e te rm in e o n e o f fo u r a c tiv e D ata

F10176

Abstract: F10576 low power T Flip-Flop
Contextual Info: F10176^ F 10576^ HIGH SPEED HEX D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL D E S C R IP TIO N — The F10176 and F10576 c o n ta in six high -spe ed m aster/slave D type flip -flo p s w h ic h have a c o m m o n C lo ck. D ata is entered in to the m aster w hen the C lock

F10176

Contextual Info: F 1 0 1 7 6 • F 1 0 5 7 6 HIGH SPEED HEX D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL DESCRIPTIO N— The F10176and F10576 contain six high-speed master/slave D type flip -flop s which have a comm on Clock. Data is entered into the master when the Clock is LOW. Data transfer takes place on the positive-going clock transition. A change in the

L1319

Contextual Info: F10173 • F10573 QUAD MULTIPLEXER/LATCH DESCRIPTION — The F10173 and F10573 are Quad 2-Channel Multiplexers with LOGIC SYMBOL latches. They incorporate a common Enable and a common Data Select Input. The Select input determines which Data input is enabled. A HIGH input enables Data inputs

Contextual Info: F10175 • F10575 QUINT LATCH DESCRIPTION —The F10175 and F10575 are high-speed low-power Quint Latches. They feature five D type latches with common Reset and a common 2-input Enable. Data is transferred on the negative edge of the enable and latched on the positive edge.

STK 442 - 130

Abstract: stk 412 -130 BT 342 project ID78K0S-NS IE-78K0S-NS IE-78K0S-NS-A RA78K0S stk 412 - 240 STK 412 240 stk 412 170
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