EDS2532AABJ Search Results
EDS2532AABJ Datasheets (6)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
---|---|---|---|---|---|---|---|
EDS2532AABJ-6B |
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256M bits SDRAM (8M words x 32 bits) | Original | 621.38KB | 48 | ||
EDS2532AABJ-6B-E |
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256M bits SDRAM (8M words x 32 bits) | Original | 621.39KB | 48 | ||
EDS2532AABJ-6BL-E |
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256M bits SDRAM (8M words x 32 bits) | Original | 621.38KB | 48 | ||
EDS2532AABJ-75 |
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256M bits SDRAM (8M words x 32 bits) | Original | 644.74KB | 48 | ||
EDS2532AABJ-75-E |
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256M bits SDRAM (8M words x 32 bits) | Original | 644.74KB | 48 | ||
EDS2532AABJ-75L-E |
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256M bits SDRAM (8M words x 32 bits) | Original | 644.74KB | 48 |
EDS2532AABJ Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
---|---|---|---|
EDS2532AABJ-6BContextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-6B 8M words x 32 bits Description Pin Configurations The EDS2532AABJ is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2532AABJ-6B EDS2532AABJ 90-ball 166MHz M01E0107 E0509E30 EDS2532AABJ-6B | |
EDS2532AABJ-6BContextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-6B 8M words x 32 bits Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2532AABJ-6B 90-ball 166MHz cycles/64ms M01E0107 E0509E40 EDS2532AABJ-6B | |
EDS2532AABJ-75Contextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-75 8M words x 32 bits Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2532AABJ-75 90-ball 133MHz cycles/64ms M01E0107 E0508E40 EDS2532AABJ-75 | |
EDS2532AABJ-75Contextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-75 8M words x 32 bits Description Pin Configurations The EDS2532AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2532AABJ-75 EDS2532AA 90-ball 133MHz M01E0107 E0508E30 EDS2532AABJ-75 | |
Contextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-6B 8M words x 32 bits Description Pin Configurations The EDS2532AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2532AABJ-6B EDS2532AA 90-ball 166MHz M01E0107 E0509E20 | |
Contextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-75 8M words x 32 bits Description Pin Configurations The EDS2532AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2532AABJ-75 EDS2532AA 90-ball 133MHz M01E0107 E0508E20 | |
EDS2532AABJ-6BContextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-6B 8M words x 32 bits Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2532AABJ-6B 90-ball 166MHz cycles/64ms M01E0107 E0509E40 EDS2532AABJ-6B | |
90-Ball
Abstract: ECA-TS2-0096-01
|
Original |
EDS2532AABJ-6B 90-ball ECA-TS2-0096-01 E0509E30 ECA-TS2-0096-01 | |
EDS2532AABJ-75Contextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-75 8M words x 32 bits Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2532AABJ-75 90-ball 133MHz cycles/64ms M01E0107 E0508E40 EDS2532AABJ-75 |