DS717 Search Results

Contextual Info: LogiCORE IP Multiply Adder v3.0 DS717 March 20, 2013 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Multiply Adder core provides implementations of multiply-add using DSP slices. It performs a multiplication of two operands and adds or

139-2 "cross reference"

Abstract: ANA 618 AIN348 AIN452 CS42888 CS5341 CS8416
Contextual Info: CS42888 108 dB, 192 kHz 4-In, 8-Out CODEC FEATURES GENERAL DESCRIPTION  Four 24-bit A/D, Eight 24-bit D/A Converters The CS42888 CODEC provides four multi-bit analog-todigital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a

AIN348

Abstract: AIN452 CS42888 CS5341 CS8416
Contextual Info: CS42888 108 dB, 192 kHz 4-In, 8-Out CODEC FEATURES GENERAL DESCRIPTION  Four 24-bit A/D, Eight 24-bit D/A Converters The CS42888 CODEC provides four multi-bit analog-todigital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a

67C97

Abstract: DBit12
Contextual Info: 3 635 D D6 1 233 45 6 7 8 9 A B C 9 B D 7 E F F  9 B  63  D 7  C 9 9   6   6 F    F 6  B 6  C  9 8 A B   A 3 69FC6AFB89 4 6 6!CBEFA D ! ' 

64814ESTM4G12T

Abstract: PC-100 PC100 1998
Contextual Info: 8M x 64 Bit Registered PC-100 SDRAM DIMM Registered PC-100 SYNCHRONOUS DRAM DIMM 64814ESTM4G12T 168 Pin 8Mx64 SDRAM DIMM Registered, 4k Refresh, 3.3V with SPD Pin Assignment General Description Pin# The module is an 8Mx64 bit, 12 chip, 168 Pin DIMM module consisting of

Contextual Info: CS42888 108 dB, 192 kHz 4-In, 8-Out CODEC FEATURES GENERAL DESCRIPTION Ł Four 24-bit A/D, Eight 24-bit D/A Converters The CS42888 CODEC provides four multi-bit analog-todigital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a

EUP7171DIR1

Abstract: EUP7171 EUP7171DIT1
Contextual Info: EUP7171 2A Sink/Source Bus Termination Regulator DESCRIPTION FEATURES The EUP7171 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching

Contextual Info: CS42888 108 dB, 192 kHz 4-In, 8-Out CODEC FEATURES GENERAL DESCRIPTION  Four 24-bit A/D, Eight 24-bit D/A Converters The CS42888 CODEC provides four multi-bit analog-to-digital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs

Contextual Info: CS42888 108 dB, 192 kHz 4-In, 8-Out CODEC FEATURES GENERAL DESCRIPTION  Four 24-bit A/D, Eight 24-bit D/A Converters The CS42888 CODEC provides four multi-bit analog-todigital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a