CY7C266 Search Results

C2665

Abstract: C2668 7c26 C2662 C266 27C64 CY7C266 R1250 C2666
Contextual Info: 1CY 7C26 6 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

CY7C2663KV18

Abstract: CY7C2665KV18 3M Touch Systems CY7C2663KV18-450BZXC
Contextual Info: CY7C2663KV18, CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

LC 7258

Abstract: 7C266 203CE
Contextual Info: CY7C266 / CYPRESS 8K x 8 Power-Switched and Reprogrammable PROM Features • TTL-compatible I/O • CMOS for optimum speed/power • Direct replacement for 27C64 EPROMs • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military)

27C64

Abstract: CY7C266 R1250 direct replacement
Contextual Info: 66 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) The CY7C266 is a high-performance 8192 word by 8 bit

LC 7258

Abstract: AG04
Contextual Info: ^ CY7C266 SEMICONDUCTOR 8K x 8 PROM PowerSwitched and Reprogrammable Features • TTL-compatible I/O • CMOS for optimum speed/power • Direct replacement for 27C64 EPROMs • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military)

27C64

Abstract: CY7C266 R1250 8kx8 eprom pin diagram
Contextual Info: CY7C266 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features powers down into a low-power standby mode. It is packaged in a 600-mil-wide package. The reprogrammable packages are equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells utilize proven EPROM

Contextual Info: CY7C266 CYPRESS 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power The CY7C266 is a high-performance 8192 word by 8 bit CMOS PROM. When deselected, the CY7C266 automatically powers down into a low-power standby mode. It is packaged

Contextual Info: CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features powers down into a low-power standby mode. It is packaged in a 600-mil-wide package. The reprogrammable packages are equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells utilize proven EPROM

Contextual Info: CY7C2663KV18/CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

p20d

Abstract: CERPAK data retention eprom Cypress 7c26 CY7C261 CY7C263 CY7C264 CY7C266 CY7C269 EME-6300H
Contextual Info: Qualification Report March, 1992 QTP 91296 Version 1.0 64K EPROM FAMILY, 0.8µ MARKETING PART NUMBER DEVICE DESCRIPTION CY7C261 8K x 8 POWER-SWITCHED CY7C263 8K x 8 CY7C264 8K x 8 600-MIL PKG CY7C266 8K x 8 POWER-SWITCHED EPROM PINOUT CY7C269 8K x 8 REGISTERED DIAGNOSTIC

Contextual Info: CY7C266 CYPRESS SEMICONDUCTOR Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 mW (military) • Super low standby power — Less than 85 mW when deselected

Contextual Info: CY7C2663KV18/CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

3M Touch Systems

Abstract: CY7C2663KV18-450BZXC
Contextual Info: CY7C2663KV18, CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

Contextual Info: _ CY7C266 c y p p f^ s = W SEMICONDUCTOR Features • CMOS for optimum speed/power • Windowed for reprogrammablUty • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 mW (military)

Contextual Info: CY7C266 PRELIM INARY CYPRESS SEMICONDUCTOR 8192 x 8 PROM Power Switched and Reprogrammable Features • CMOS for optimum speed/power • Direct replacement for EPROMs • Windowed for reprogrammability • Capable of withstanding > 2000V static discharge • High speed

Contextual Info: _ CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • C M O S fo r o p tim u m sp ee d /p o w e r T he C Y 7C 266 is a hig h -p e rfo rm a n ce 8192 w o rd by 8 bit C M O S PRO M . W hen de selected , th e C Y 7C 266 a u to m a tica lly

C266

Abstract: P15 Package 27C64 CY7C266 R1250 8kx8 eprom pin diagram
Contextual Info: ,.V.Ï .Ï .V.^ y nr' Æ CY7C266 CYPRESS 8Kx8 Power-Switched and Reprogrammable PROM Functional Description Features • CMOS fo r optimum speed/power • Windowed for reprogramm ability • High speed The CY7C266 is a high-performance 8192 word by 8 bit CMOS PROM. When deselected, the CY7C266 automatically

Contextual Info: CY7C266 ^ 0 CYPRESS 8K x 8 Power-Switched and Reprogrammable PROM Features • TT L -com patible I/O • CMOS for optimum speed/power • D irect replacem ent for 27C64 E PR O M s • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military)

27C64

Abstract: CY7C266 R1250 LP 06 A4 A1 AA
Contextual Info: ,.V.Ï.Ï.V.^ y nr' Æ CY7C266 CYPRESS 8Kx8 Power-Switched and Reprogrammable PROM Functional Description Features • CMOS fo r optimum speed/power • Windowed for reprogramm ability • High speed The CY7C266 is a high-performance 8192 word by 8 bit CMOS PROM. When deselected, the CY7C266 automatically

Contextual Info: 66 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features powers down into a low-power standby mode. It is packaged in a 600-mil-wide package. The reprogrammable packages are equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells utilize proven EPROM

3M Touch Systems

Abstract: CY7C2663KV18-450BZXC
Contextual Info: CY7C2663KV18, CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

3M Touch Systems

Contextual Info: CY7C2666KV18, CY7C2677KV18 CY7C2668KV18, CY7C2670KV18 144-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 144-Mbit density (16 M x 8, 16 M × 9, 8 M × 18, 4 M × 36)

3M Touch Systems

Abstract: CY7C2663KV18-450BZXC
Contextual Info: CY7C2661KV18, CY7C2676KV18 CY7C2663KV18, CY7C2665KV18 144-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

333Q

Abstract: 27C64 CY7C266 a50tb
Contextual Info: CY7C266 5 f C Y PR ESS 8K x 8 Power-Switched and Reprogrammable PROM Features • TTL-compatible I/O • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Direct replacement for 27C64