CY7C1270XV18 Search Results

CY7C1270XV18 Datasheets (2)

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Cypress Semiconductor

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C1270XV18-600BZXC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 600MHZ 165FBGA	Original	PDF		28
CY7C1270XV18-633BZXC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 633MHZ 165FBGA	Original	PDF		28

CY7C1270XV18 Price and Stock

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Cypress Semiconductor


Cypress Semiconductor CY7C1270XV18-633BZXC SRAM Chip Sync Single 1.8V 36M-bit 1M x 36 0.45ns 165-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical	CY7C1270XV18-633BZXC		125		25	1 - 10 - 100 $114.24 1000 $102.21 10000 $96.20	Buy Now
Rochester Electronics	CY7C1270XV18-633BZXC		125		1	1 - 10 - 100 $91.39 1000 $81.77 10000 $76.96	Buy Now
Cypress Semiconductor CY7C1270XV18-600BZXC CY7C1270XV18-600BZXC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical ()	CY7C1270XV18-600BZXC		89		25	1 - 10 - 100 $113.76 1000 $101.79 10000 $95.80	Buy Now
	CY7C1270XV18-600BZXC		79		25	1 - 10 - 100 $113.76 1000 $101.79 10000 $95.80	Buy Now
Rochester Electronics	CY7C1270XV18-600BZXC		168		1	1 - 10 - 100 $91.01 1000 $81.43 10000 $76.64	Buy Now

CY7C1270XV18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY7C1268XV18/CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 cycles:	Original	CY7C1268XV18/CY7C1270XV18 36-Mbit CY7C1268XV18 CY7C1270XV18	PDF
Contextual Info: CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)	Original	CY7C1268XV18, CY7C1270XV18 36-Mbit CY7C1268XV18	PDF
3M Touch Systems Contextual Info: CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 cycles:	Original	CY7C1268XV18, CY7C1270XV18 36-Mbit CY7C1268XV18 3M Touch Systems	PDF
3M Touch Systems Contextual Info: CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)	Original	CY7C1268XV18, CY7C1270XV18 36-Mbit CY7C1268XV18 3M Touch Systems	PDF