CY7C1170V18 Search Results

Contextual Info: CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 400 MHz clock for high bandwidth

Contextual Info: CY7C1168V18 CY7C1170V18 PRELIMINARY 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 18-Mbit density (1M x 18, 512K x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency

CY7C1166V18

Abstract: CY7C1168V18 CY7C1170V18 CY7C1177V18
Contextual Info: CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 400 MHz clock for high bandwidth

Contextual Info: CY7C1177V18 CY7C1168V18 CY7C1170V18 PRELIMINARY 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit density (2M x 9, 1M x 18, 512K x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

CY7C1166V18

Abstract: CY7C1168V18 CY7C1170V18 CY7C1177V18
Contextual Info: CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 400 MHz clock for high bandwidth

3M Touch Systems

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06620 Spec Title: CY7C1166V18/CY7C1177V18/CY7C1168V18/ CY7C1170V18, 18-MBIT DDR-II+ SRAM 2-WORD BURST ARCHITECTURE 2.5 CYCLE READ LATENCY Sunset Owner: Jayasree Nayar (NJY) Replaced by: None CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18