CY7C09179V Search Results

A15LC

Abstract: A14L A14LC A12LC CY7C09099V 751V
Contextual Info: “ tv * I PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow sim ulta­ neous access of the same memory location • 6 Flow-Through/Pipelined devices

CY7C09099V

Contextual Info: fax id: 5210 PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synch ronous Dual-Port Static RAM Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same memory location • 6 Flow-Through/Pipelined devices

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V 1CY7C025/0251 CY2411 54-MHz MPEG Clock Generator with VCXO 2 Features Benefits • Integrated phase-locked loop Highest Performance PLL tailored for multimedia applications • Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs

CY7C09099V

Contextual Info: 1 CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079V/179V

CY7C09099V

Contextual Info: 51 PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079V/179V

CY24119

Abstract: CY24119-1 CY24119SC CY24119SC-1 CY24119SCT
Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY24119 PRELIMINARY MediaClock 27-MHz VCXO Clock Generator Features Benefits • Low-jitter, high-accuracy output • Meets critical timing requirements in complex system designs • VCXO with analog adjust • Large ± 150 ppm range, better linearity

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max. True Dual-Ported memory cells which enable simultaneous

CY7C09099V

Abstract: 8-9V
Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max. True Dual-Ported memory cells which enable simultaneous

CY7C09099V

Contextual Info: 1 PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079V/179V

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

CY7C09099V

Contextual Info: fax id: 5210 CYPRESS CY7C09079V/89V/99V CY7C09179V/89V/99V PRELIMINARY 3.3V 32K/64K/128K x 8/9 Synchronous Dual Port Static RAM Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location • 6 Flow-Through/Pipelined devices

CY7C09099V

Abstract: hcn 73
Contextual Info: fax id: 5210 CYPRESS PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location • 6 Flow-Through/Pipelined devices

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V 1CY7C025/0251 CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices

CY7C09099V

Contextual Info: P R E L IM IN A R Y CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • 6 Flow-Through/Pipelined devices

0702C

Abstract: CY7C09099V
Contextual Info: fax id: 5210 '•'■'■'■'■'■'■‘JJSt>iW.-. a S S K , : 'S^ì,„*$ & :*■ _ jg ? CY7C09079V/89V/99V CY7C09179V/89V/99V PRELIMINARY . "T 3.3V 32K/64K/128K x 8/9 Synchronous Dual Port Static RAM • 0.35-micron CMOS for optimum speed/power

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max. True Dual-Ported memory cells which enable simultaneous

CY7C09099V

Abstract: A10FL
Contextual Info: fax id: 5210 CYPRESS PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual Port Static RAM Features 0.35-mlcron CMOS for optimum speed/power High-speed clock to data access 10/12 ns max. 3.3V Low operating power • True Dual-Ported memory cells which allow simulta­

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09099V CY7C09179V 3.3 V 32K/128K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which enable simultaneous access of the same memory location

7C038VA

Abstract: R42HD Hitachi-CEL9200 CY7C09099V
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98516 VERSION 1.1 October, 1999 Low Voltage Synchronous/Asynchronous Dual Port SRAM R42D Technology, Fab 4 Qualification CY7C09079V/CY7C09179V 32K x 8/9 Synchronous DP SRAM CY7C09089V/CY7C09189V 64K x 8/9 Synchronous DP SRAM

CY24119

Abstract: CY24119-1 CY24119SC CY24119SC-1 CY24119SCT VCXO 27MHZ
Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY24119 PRELIMINARY MediaClock 27-MHz VCXO Clock Generator Features Benefits • Low-jitter, high-accuracy output • Meets critical timing requirements in complex system designs • VCXO with analog adjust • Large ± 150 ppm range, better linearity

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V 1CY7C025/0251 LVDS vs. Low Voltage Differential Signaling Purpose While the phrase “Low Voltage Differential Signling for Interface Circuilts” LVDS often implies a high-performance, high-speed communication channel that is completely specified by that single phrase, in reality the term “LVDS” does not,