CY37192VP Search Results

ASE BGA

Abstract: tsmc mos 45 7C37655B CY37256
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 99457 Revision 1.3 September 2000 High-Performance CPLDs Family CY37192P CY37192VP UltraLogic 192 Macrocell ISR™ CPLDs CY37256P CY37256VP UltraLogic™ 256 Macrocell ISR™ CPLDs CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os

tlp 453

Contextual Info: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant

Contextual Info: CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD Features — tpD = 12 ns — ts = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6 .5 ns • Product-term clocking — 3.3V ISR • IEEE 1149.1 JTAG boundary scan

clcc land pattern

Abstract: CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern
Contextual Info: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37512P208-100UMB

Abstract: CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37064P44-154YMB CY37512P208-100UMB
Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

l0249

Abstract: CY37032VP44-100AI
Contextual Info: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

5962-9951902QYA

Abstract: CY37128P100-125AXC U208 5962-9952301QZC CERAMIC LEADLESS CHIP CARRIER CY37032P44-125JXC CY37512P256-100BGI CY37192 CY37256 CY37384
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

Contextual Info: CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12.0 ns Features — tS = 7.0 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37032VP44-100AI

Abstract: 5962-9952502QZC 400BA
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37064P44-154YMB
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37256P160-125AXI

Abstract: CY37032P44-125JXC 5962-9952502QZC CY37128P100-125AXC CY37032V 5962-9952301QZC 5962-9952302QZC CY37064P100-125AXI CY37512VP208-66NI tea1400
Contextual Info: Ultra37000 CPLD Family 5V and 3.3V ISR High Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs ❐ JTAG interface for reconfigurability ❐ Design changes do not cause pinout changes ❐ Design changes do not cause timing changes

ncl016

Contextual Info: •gg P R E L IM IN A R Y ^^^B88888888888888888888SSi^ Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking

CY37064

Abstract: ULTRA37000 CY37032 CY37032V CY37064V CY37128 CY37128V CY37192 CY37256 CY37384
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

CY37192

Abstract: CY37192V
Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37032P44-154AXI

Abstract: CY37128P160-125AC 5962-9951902QYA CY37032 CY37032V CY37064 CY37064V CY37128 CY37128V CY37192
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

CY37192

Abstract: CY37192V cypress ultra37000 jtag
Contextual Info: ww.vi fv«/ kvv' UltraLogic 3.3V 192-Macrocell ISR™ CPLD — ts = 7.0 ns Features — tco = 6.0 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37192

Abstract: CY37192V
Contextual Info: Back PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37032VP44-100AI

Abstract: CY37512P208-100UM CY37512P208-100UMB CY37064P44-154YMB
Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37128P100-125AXC
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

Contextual Info: Ultra37000 CPLD Family 5 V and 3.3 V ISR High Performance CPLDs 5 V and 3.3 V ISR™ High Performance CPLDs General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs ❐ JTAG interface for reconfigurability ❐ Design changes do not cause pinout changes

CY37064P44-154YMB

Abstract: CY37512P208-100UMB CY37256P160-125UMB CY37032 CY37032V CY37064 CY37064V CY37128 CY37128V CY37032VP44-100AI
Contextual Info: Family Ultra37000 CPLD Family[1] 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes