CY2DP1510 Search Results

Contextual Info: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to 10 LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL

Input voltage 40V Output voltage 13.8V

Abstract: JEDEC SPEC MS - 034 JESD78B
Contextual Info: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage positive emitter-coupled logic LVPECL input pairs to distribute to 10 LVPECL output pairs ■ 40-ps maximum output-to-output skew