CD74FCT273 Search Results

CD74FCT273

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

CD74FCT273

Abstract: CD74FCT273E CD74FCT273M
Contextual Info: CD74FCT273 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCH S254 BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset January 1997 Features Circuit Design \Jse ' Speed of Bipolar FAST /AS/S Buffered Inputs 48mA Output Sink Current

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

chn 834

Abstract: CD74FCT273 CD74FCT273E CD74FCT273M Chn 835
Contextual Info: CD74FCT273 S E M I C O N D U C T O R January 1997 D ENDE M M ECO IGNS NOT R NEW DES ology FOR OS Techn BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset M Features Use C Description The CD74FCT273 octal D flip-flop with reset uses a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

74FCT273M

Contextual Info: CD74FCT273 S em iconductor January 1997 SÜSS »? W &M \jse C W \O S BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset TecW Features Description • Buffered Inputs The CD74FCT273 octal D flip-flop with reset uses a small geom etry BiCMOS technology. The output stage is a com ­

Contextual Info: CD74FCT273 ^ Te x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCH S254 BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset January 1997 Features NENN TecW \Jse GVvAOS Circuit Design Speed of Bipolar FAST /AS/S Buffered Inputs

Contextual Info: a CD74FCT273T, T2273T H A R R is S E M I C O N D U C T O R Fast CMOS Octal D Flip-Flop with Master Reset September 1996 Features Description • Advanced 0.8 micron CMOS Technology • These Devices are Pin Compatible with Bipolar FAST Series at a Higher Speed and Lower Power

Contextual Info: if H A R R CD74FCT273 IS S E M I C O N D U C T O R January 1997 BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset t & SQSM& E 'Ni OrT w no\ogv Features Description • Buffered Inputs The CD74FCT273 octal D flip-flop with reset uses a small geometry BiCMOS technology. The output stage is a com­

CD74FCT273CTQM

Abstract: CD74FCT2273T CD74FCT273ATM CD74FCT273ATQM CD74FCT273CTM CD74FCT273DTM CD74FCT273T CD74FCT273TM CD74FCT273TQM
Contextual Info: CD74FCT273T, CD74FCT2273T S E M I C O N D U C T O R Fast CMOS Octal D Flip-Flops with Master Reset December 1996 Features Description • Advanced 0.8 micron CMOS Technology • These Devices are Pin Compatible with Bipolar FAST Series at a Higher Speed and Lower Power

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

CD74FCT273

Abstract: CD74FCT273E CD74FCT273EE4 CD74FCT273M CD74FCT273M96 CD74FCT273M96E4 CD74FCT273M96G4 CD74FCT273ME4
Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: CD74FCT273 Œ January 1997 SÜSS »? W & iï \jse GVJ\OS BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset TecW Features Description • Buffered Inputs The CD74FCT273 octal D flip-flop with reset uses a small geom etry BiCMOS technology. The output stage is a com ­

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: h a fr fr is CD74FCT273T, CD74FCT2273T S E M I C O N D U C T O R Fast CMOS Octal D Flip-Flop with Master Reset December 1996 Features Description • Advanced 0.8 micron CMOS Technology The CD74FCT273T and CD74FCT2273T are 8-bit wide octal designed with eight edge-triggered D-type flip-flops

Contextual Info: CD74FCT273T, CD74FCT2273T îü HARRIS S E M I C O N D U C T O R Fast CMOS Octal D Flip-Flops with Master Reset December 1996 Features Description • Advanced 0.8 micron CMOS Technology The CD74FCT273T and CD74FCT2273T are 8-bit wide octal designed with eight edge-triggered D-type flip-flops

CD74FCT273

Abstract: CD74FCT273E CD74FCT273EE4 CD74FCT273M CD74FCT273M96 CD74FCT273M96E4 CD74FCT273M96G4 CD74FCT273ME4
Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

CD74FCT273

Abstract: CD74FCT273E CD74FCT273EE4 CD74FCT273M CD74FCT273M96 CD74FCT273M96E4 CD74FCT273ME4
Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

Contextual Info: CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE TOP VIEW BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V

CD74FCT273

Abstract: CD74FCT273E CD74FCT273M
Contextual Info: CD74FCT273 Data sheet acquired from Harris Semiconductor SCHS254 January 1997 Features BiCMOS FCT Interface Logic, Octal D Flip-Flop with Reset D ENDE M M O S EC IGN NOT R NEW DES ology FOR OS Techn M Use C • • • • • • • Buffered Inputs • Typical Propagation Delay: 5.3ns at VCC = 5V,