BB256 Search Results

100-Ball

Abstract: 288-ball
Contextual Info: Package Diagrams Thin Ball Grid Array Packages 100-Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85107 1 Package Diagrams 165-Ball FBGA (13 x 15 x 1.35 mm) BB165 51-85122 2 Package Diagrams 172-Ball FBGA BB172 51-85114 3 Package Diagrams 256-Ball Thin Ball Grid Array (17 x 17 mm) BB256

Contextual Info: ADVANCE INFORMATION 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES 16 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits • • • FEATURES: • • • • • • • • • • • • Choose from among the following memory density options:

Contextual Info: ADVANCE INFORMATION IDT72T51333 IDT72T51343 IDT72T51353 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES 8 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits • • • • FEATURES: • • • • • • • • • • • Choose from among the following memory density options:

CYD01S36V

Abstract: CYD02S36V CYD04S36V CYD09S36V CYD18S36V 1.0mm pitch BGA
Contextual Info: CYD01S36V CYD02S36V/CYD04S36V CYD09S36V/CYD18S36V PRELIMINARY FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and

IDT72T51236

Abstract: IDT72T51246 IDT72T51256
Contextual Info: 2.5V MULTI-QUEUE FIFO 4 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51236  Total Available Memory = 589,824 bits

72T51436

Abstract: 72T51446 IDT72T51436 IDT72T51446 IDT72T51456 multi-queue
Contextual Info: 2.5V MULTI-QUEUE FIFO 16 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51436  Total Available Memory = 589,824 bits

IDT72T51333

Abstract: IDT72T51343 IDT72T51353
Contextual Info: 2.5V MULTI-QUEUE FIFO 8 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51333  Total Available Memory = 589,824 bits

72T51546

Abstract: 72T51556 IDT72T51546 IDT72T51556
Contextual Info: 2.5V MULTI-QUEUE FIFO 32 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits FEATURES: • • • • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51546  Total Available Memory = 1,179,648 bits

IDT72V51433

Abstract: IDT72V51443 IDT72V51453
Contextual Info: 3.3V MULTI-QUEUE FLOW-CONTROL DEVICES 16 QUEUES 18 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits • • • • FEATURES: • • • • • • • • • • Choose from among the following memory density options: IDT72V51433  Total Available Memory = 589,824 bits

clcc land pattern

Abstract: CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern
Contextual Info: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

5B1 International Rectifier

Abstract: 446H BE 4CA diode BFE 75A 451H 729h 751H BFE 73A INTERNATIONAL RECTIFIER 432h S4 6ba
Contextual Info: Octal T1/E1/J1 Long Haul / Short Haul Transceiver IDT82P2288 Version April 25, 2003 2975 Stender Way, Santa Clara, Califormia 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 2001 Integrated Device Technology, Inc.

Contextual Info: 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES 32 QUEUES 18 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits • • • FEATURES: • • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51543  Total Available Memory = 1,179,648 bits

Contextual Info: 3.3V MULTI-QUEUE FLOW-CONTROL DEVICES 32 QUEUES 36 BIT WIDE CONFIGURATION IDT72V51546 IDT72V51556 1,179,648 bits 2,359,296 bits • • FEATURES: • • • • • • • • • • • • Choose from among the following memory density options: IDT72V51546  Total Available Memory = 1,179,648 bits

CY37512P208-100UMB

Abstract: CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37064P44-154YMB CY37512P208-100UMB
Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: FullFlex FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

IDT72V7250

Abstract: IDT72V7260 IDT72V7270 IDT72V7280 IDT72V7290 IDT72V72100 IDT72V7230 IDT72V7240 are d68 hf no 72V7250
Contextual Info: 3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72 • • • FEATURES: • • • • • • • Choose among the following memory organizations: IDT72V7230  512 x 72

38K30

Abstract: DELTA39K
Contextual Info: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and

IDT72T51336

Abstract: IDT72T51346 IDT72T51356
Contextual Info: PRELIMINARY IDT72T51336 IDT72T51346 IDT72T51356 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES 8 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits • • • FEATURES: • • • • • • • • • • • • Choose from among the following memory density options:

IDT72T51236

Abstract: IDT72T51246 IDT72T51256
Contextual Info: PRELIMINARY IDT72T51236 IDT72T51246 IDT72T51256 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES 4 QUEUES 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits • • FEATURES: • • • • • • • • • • • • Choose from among the following memory density options:

FullFlex36

Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

psoc c code for ring counter

Contextual Info: CYD02S36V/36VA FLEx36 3.3 V 64K x 36 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that enable simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Pipelined output mode allows fast operation