AD6122 Search Results

Contextual Info: CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 ANALOG DEVICES FEATURES Fully Com pliant w ith IS98A and PCS Specifications Linear IF A m plifier -6 3 dB to +34 dB Linear-in-dB Gain Control Tem perature-Com pensated Gain Control

AD6122

Abstract: AD6122ARS AD6122ARSRL AD830 HP34970A HPE3610 IS98A SMT03 specifications of DAC 1408 HP8116A
Contextual Info: a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator

smt03

Abstract: collector modulator HP8116A AD6121 AD6122 AD6122ACP AD6122ACPRL AD6122ARS AD6122ARSRL AD830
Contextual Info: a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator

HP81

Contextual Info: a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control with a nominal 75 dB/V scale factor. Either an internal or an external

HP8116A

Abstract: AD6121 AD6122 AD6122ARS AD6122ARSRL AD830 HPE3610 IS98A SMT03 video balun
Contextual Info: a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator

6122m

Contextual Info: CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 ANALOG DEVICES FEATURES Fully Com pliant w ith IS98A and PCS Specifications Linear IF A m plifier -6 3 dB to 4-34 dB Linear-in-dB Gain Control Tem perature-Com pensated Gain Control

Contextual Info: CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 ANALOG DEVICES FEATURES Fully Com pliant w ith IS98A and PCS Specifications Linear IF A m plifier -6 3 dB to +34 dB Linear-in-dB Gain Control Tem perature-Com pensated Gain Control

313MHz

Abstract: collector modulator
Contextual Info: a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator

AD9763

Abstract: AD9763AST AD9763-EB AWG2021
Contextual Info: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 mHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

48-PIN

Abstract: AD9709 AD9709AST AD9709-EB AWG2021
Contextual Info: a FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

DAC89EX

Abstract: dac86ex RBS 2111 ad42497 DAC0803 RBS 2101 ad429 AD427 AD4249 AD6422
Contextual Info: ADSP-2100 Family DSP Microcomputers ADSP-21xx a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter

HP8508A

Abstract: smt03 Tektronix tds 210 FMMT4403CT-ND 32-leadless SMT-03 AD6121A HPE3610 dc/TDA 8538
Contextual Info: a CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator AD6121 FEATURES Fully Compliant with IS98A and PCS Specifications CDMA, W-CDMA, AMPS, and TACS Operation Linear IF Amplifier 5.9 dB Noise Figure –47.5 dB to +47 dB Linear-in-dB Gain Control

AD9754

Contextual Info: a 14-Bit, 125 MSPS High Performance TxDAC D/A Converter AD9754* FEATURES High Performance Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 14-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 83 dBc

AD9744

Abstract: AD9744-AR AD9744-ARU AD9744-EB DB10 RU-28 I-V amplifier minicircuits t1-1t 32RL
Contextual Info: PRELIMINARY TECHNICAL DATA a 14-Bit, 165 MSPS TxDAC D/A Converter AD9744 Preliminary Technical Data FEATURES +3V REFLO AVDD REFIO FSADJ Wideband Communications TX: Digital Quadrature Modulation Architectures W-CDMA, Multi-Carrier GSM, TDMA, CDMA Systems

34B DBM

Abstract: AD9754 capacitor 100MF 100v if transformer 455khz AD9754AR AD9754ARU AD9754-EB DB10 RU-28
Contextual Info: a 14-Bit, 125 MSPS High Performance TxDAC D/A Converter AD9754* FEATURES High Performance Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 14-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 83 dBc

AD9767

Abstract: AD9767AST AD9767-EB
Contextual Info: a FEATURES 14-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 82 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

C8380

Abstract: AD804 AD9765 AD97651 AD9765AST AD9765-EB
Contextual Info: a FEATURES 12-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

Contextual Info: a Preliminary Technical Data FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 67 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference

pt 8538

Contextual Info: RF/IF: IF Receivers, Transmitters Transceivers IF SUBSYSTEMS: RECEIVERS <<<<<<<<<< Mixer Input >>>>>>>> RF 1dB Range I3P Comp NF MHz dBm dBm dB Model Vss +V Iss mA AD608 2.7 7.3 Model Vss +V Iss mA AD607 2.7 8.5 500 AD6432 2.7 8 350 AD6121 2.7 10 NA AD6459

ssm-2126A

Abstract: TETRA ACELP AD22151 AD698 DAC8842 AD7874 SSM-2125A AD6439 ad53042 AD9851
Contextual Info: GENERAL PURPOSE COMPONENTS OVERVIEW A/D CONVERTERS AMPLIFIERS OVERVIEW OVERVIEW <1 MSPS Single Supply >1 MSPS <20 >20 MSPS Sigma-Delta Low Bias Current Matched Transistors NPN and PNP Single Supply High Speed Instrumentation Codecs and I/O Ports MicroConverters

Contextual Info: Analog Devices in CDMA Introductory Section for February 2000 CD-ROM ADI CDMA Intro - CDROM - February 2000 Slide 1 ADI CDMA Activities ! IS-95 CDMA cdmaOne " 1st Generation BiCMOS IF ICs, CMOS Custom Baseband ICs " All functions migrating to CMOS in next generation

Contextual Info: ANALOG DEVICES CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator AD6121 FEATURES Fully C om pliant w ith IS98A and PCS Specifications CDMA, W-CDMA, AMPS and TACS O peration Linear IF A m plifier 5.9 dB Noise Figure -47.5 dB to +47 dB Linear-in-dB Gain Control

C3582a-0-2

Abstract: AD9763 AD9763AST AD9763-EB AWG2021 transmission line transformer
Contextual Info: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 78 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

HP8508A

Abstract: smt03 HP8116A C3438 AD6121 AD6121ARS AD6121ARSRL AD6122 AD830 HP34970A
Contextual Info: a CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator AD6121 FEATURES Fully Compliant with IS98A and PCS Specifications CDMA, W-CDMA, AMPS and TACS Operation Linear IF Amplifier 5.9 dB Noise Figure –47.5 dB to +47 dB Linear-in-dB Gain Control