9L RESET Search Results

HFBR-1521

Abstract: 217KH
Contextual Info: 6.+,  : 6.+,  $EVROXWH 0D[LPXP 5DWLQJV 6\PERO 7HUP 9DOXHV 8QLWV 96 9L+ ,RXW3 $. ,RXW$9PD[ IPD[ 9&( 6XSSO\ YROWDJH SULPDU\ VLGH ,QSXW VLJQDO YROWDJH +LJK 2XWSXW SHDN FXUUHQW 2XWSXW DYHUDJH FXUUHQW PD[7DPE ƒ& VZLWFKLQJ IUHTXHQF\ PD[ &ROOHFWRU HPLWWHU YROWDJH

tc 97101

Abstract: D472
Contextual Info: ADVANCE M IC B D N I ' I 4 MEG BURST EDO DRAM MODULE MT9LD272 B N , MT18LD472 B(N) 72 BURST ED0 DRAM MODULES 2, 4 MEG X 72 16, 32 MEGABYTE, 3.3V, ECC, BURST EDO FEATURES • • • • • • • • • 168-pin, dual-in-line memory module (DIMM) ECC pin-out

HD74AC4060

Contextual Info: HD74AC4060 •14-Stage Binary Counter Description Preliminary Pin Assignment The HD74AC4060 is a 14 stage counter, this device increments on the falling edge negative transition of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset

gu040

Contextual Info: MHS electronic June 1992 M 67130/M 67140 HI-REL DATA SHEET 1kx8 CMOS DUAL PORT RAM FEATURES ACCESS TIME MILITARY : 35 TO 55 ns max . BUSY OUTPUT FLAG ON MASTER 67130L/67140L LOW POWER 67130V/67140V VERY LOW POWER FULLY ASYNCHRO NO US O PERATIO N FROM EITHER PORT

Contextual Info: MC68302RC16 1/2 IL08 * ( VDD =+5V) C-MOS INTEGRATED MULTIPROTOCOL PROCESSOR -BOTTOM VIEW- N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 PIN NO. 1A 1B 1C 1D 1E 1F 1G 1H 1J 1K 1L 1M 1N 2A 2B 2C 2D 2E 2F 2G 2H 2J 2K 2L 2M 2N 3A 3B 3C 3D 3E

Contextual Info: Temic L67130/L67140 S e m ic o n d u c t o r s 1 K x 8 CMOS Dual Port RAM 3.3 Volt Introduction The L67130/67140 are very low power CMOS dual port static RAMs organized as 1024 x 8. They are designed to be used as a stand-alone 8 bits dual port RAM or as a

Contextual Info: Temic Semiconductors 1 K x 8 CMOS Dual Port RAM M67130/M67140 Introduction The M 67130/67140 are very low power CMOS dual port static RAMs organized as 1024 x 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or

Z86R91

Contextual Info: f Z T SCS-THOMSON Z8681 Z86R91 Ä 7# ROMLESS MICROCOMPUTERS • COMPLETE MICROCOMPUTER, 24 I/O LINES, AND UP TO 64K BYTES OF ADDRES­ SABLE EXTERNAL SPACE EACH FOR PRO­ GRAM AND DATA MEMORY ■ 143-BYTE REGISTER FILE, INCLUDING 124 GENERAL-PURPOSE REGISTERS, THREE

ACDL1811

Abstract: 4j diode
Contextual Info: Discontinued as of August 31, 2011 NS Series ACEA, ACBA, ACSA, ACKA Illuminated pushbutton, Indicators, Non-illuminated pushbutton, Selector, Key selector switches Full lineup to meet varied market needs Integrated 30 mm short body NS Series FEATURES 1. Unique “Fine-mechanism” high

Contextual Info: Revised January 1999 S E M I C O N D U C T O R TM General Description Features The CD4015BC contains two identical, 4-stage, serialinput/parallel-output registers with independent “Data” , “Clock,” and “ Reset” inputs. The logic level present at the

A12L

Abstract: A13L CY7C026A CY7C036A IDT70261
Contextual Info: 1 CY7C026A CY7C036A PRELIMINARY 16K x 16/18 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking

A12L

Abstract: A13L CY7C026A CY7C036A IDT70261
Contextual Info: 25/0251 CY7C026A CY7C036A 16K x 16/18 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking

CY7C026-15AI

Abstract: 9l reset A13L CY7C026 CY7C036 IDT70261
Contextual Info: fax id: 5223 51 CY7C026 CY7C036 PRELIMINARY 16K x 16/18 Dual-Port Static RAM Features • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking

fae 347

Abstract: CY7C026 9l reset A12L A13L CY7C036 IDT70261
Contextual Info: 1 CY7C026 CY7C036 PRELIMINARY 16K x 16/18 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking

A12L

Abstract: A13L CY7C026A CY7C036A IDT70261
Contextual Info: 25/0251 CY7C026A CY7C036A 16K x 16/18 Dual-Port Static RAM Features • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking

4MX9

Contextual Info: K7R323682M K7R321882M K7R320982M K7R320882M Preliminary 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001

k7r161882b

Abstract: K7R160982B K7R161882B-FC25 K7R163682B K7R163682B-FC16 K7R163682B-FC20 K7R163682B-FC25
Contextual Info: K7R163682B K7R161882B K7R160982B K7R160882B Advance 512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDRTM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDRTM II b2 SRAM Revision History Rev. No. 0.0 History Draft Date Remark 1. Initial document. Oct. 17. 2002

67130V

Abstract: ajr38 a9lc
Contextual Info: IlM l L 67130/L 67140 DATA SHEET 1Kx8 CMOS DUAL PORT RAM 3.3 Volt FEATURES . SINGLE 3.3 V ±0.3 VOLT POWER SUPPLY . FAST ACCESS TIME 45 NS * TO 70 NS . 67130L/67140L LOW POWER 67130V/67140V VERY LOW POWER . EXPANDABLE DATA BUS T 0 16 BITS OR MORE USING MASTER/SLAVE DEVICES WHEN USING

Contextual Info: A m 2130 1024x8 Dual-Port Static Random-Access Memory PRELIMINARY DISTINCTIVE CHARACTERISTICS • • • • • BUSY function to handle contention - Open drain for OR-tied operation Automatic power down CE Output Enable function (5E) Both ports operate independently

Contextual Info: L 67130/L 67140 DATA SHEET 1Kx8 CMOS DUAL PORT RAM 3.3 Volt FEATURES . SINGLE 3.3 V + 0.3 VOLT POW ER SU P PLY . FAST A C C E S S TIME 45 NS * TO 70 NS . 67130L/67140L LOW POWER 67130V/67140V V ER Y LOW POW ER . EXPAN D ABLE DATA BU S T 0 16 BITS OR MORE

SMD A19

Abstract: IEC55015 A19 SMD transistor
Contextual Info: UM10702 SSL2109ADB1110 120 V 9 W A19 high PF isolated LED driver demo board Rev. 1.1 — 27 June 2013 User manual Document information Info Content Keywords SSL2109ADB1110, isolated, flyback, demo board, LED driver, LED, 9 W, A19 Abstract This document describes the performance, technical data and the

Contextual Info: K7R163682B K7R161882B K7R160982B K7R160882B Preliminary 512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002

Contextual Info: VND7050AJ-E Double channel high-side driver with MultiSense analog feedback for automotive applications Datasheet - production data – Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin – Reverse battery with external components

Contextual Info: K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1