9FEB2008 Search Results

Contextual Info: THIS DRAWING IS A CONTROLLED DOCUMENT REVISIONS LTR DESCRIPTION RELEASE FOR DWN DATE PRODUCTION E C R - I 1- 0 0 6 6 6 7 APVD >9FEB2008 PW DH I 9APR20I I PW DH 2 , 70 @0 SIDE SCALE Fl7 7 T A" A SECTION B- 30:1 A SIDE ,05x45’ A- NOTES: PART A NUMBER DRAWING

SN74AHC595DR

Abstract: SN74AHC595PWR
Contextual Info: SN54AHC595, SN74AHC595 8ĆBIT SHIFT REGISTERS WITH 3ĆSTATE OUTPUT REGISTERS SCLS373I − MAY 1997 − REVISED JUNE 2004 QB QC QD QE QF QG QH GND description/ordering information The ’AHC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type