92LV1021 Search Results

DS92LV1021

Abstract: DS92LV1210 MSA28 deutsch rsm 07 deutsch rsm connector
Contextual Info: + & National Semiconductor PRELIMINARY July 1998 O / CO o General Description due to charged cable conditions. The 92LV1021 output pins may be TRI-STATE to achieve a high im pedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.

Contextual Info: 92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The 92LV1021 transforms a 10-bit wide parallel CMOS/ TTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1210 receives the

92LV1021

Abstract: AN1115
Contextual Info: 92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The 92LV1021 transforms a 10-bit wide parallel CMOS/ TTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1210 receives the