8XC152 Search Results

SDLC

Abstract: 80C152 2S15 SDLC synchronous signals
Contextual Info: Based on Intel’s 80C152 Global Serial Channel Flexible addressing schemes SDLC Controller Megafunction The SDLC controller is a synthesizable HDL megafunction providing a high-speed synchronous serial communication interface. Operation of the controller is similar to that used in the Intel 8XC152 Global Serial

Contextual Info: PR U ILDIM IDIM fflR f in te i 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER • 8K Factory Mask Programmable ROM Available ■ Superset of 80C51 Architecture ■ Multi-Protocol Serial Communication I/O Port 2.048 Mbps/2.4 Mbps Max

83C152JA

Abstract: JC JB jt
Contextual Info: ß ff ig y iM iß O A B n f 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER • 8K Factory Mask Programmable ROM Available ■ Superset of 80C51 Architecture ■ 64KB Data Memory Addressing ■ Multi-Protocol Serial Communication

Contextual Info: 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER • 8K Factory Mask Programmable ROM Available ■ ■ Superset of 80C51 Architecture Multi-Protocol Serial Communication I/O Port 2.048 Mbps/2.4 Mbps Max — SDLC/HDLC Only — CSMA/CD and SDLC/HDLC

80C152

Abstract: 80C152JB 8XC152JA 80C152JA 80C152JC 80C51 IN SDLC program
Contextual Info: 8XC152JA JB JC JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER X 8K Factory Mask Programmable ROM Available Y Superset of 80C51 Architecture Y 64KB Data Memory Addressing Y Multi-Protocol Serial Communication I O Port 2 048 Mbps 2 4 Mbps Max

Contextual Info: ß R IO ß g O M M V 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCOMPUTER • 8K Factory Mask Programmable ROM Available ■ ■ Superset of 80C51 Architecture Multi-Protocol Serial Communication I/O Port 2.048 Mbps/2.4 Mbps Max — SDLC/HDLC Only

sdlc

Abstract: nrzi to nrz circuit diagram 8 bit data encoder 80C152 SDLC synchronous signals IN SDLC PROTOCOL core
Contextual Info: Based on Intel’s 80C152 Global Serial Channel Flexible addressing schemes SDLC Controller Core The SDLC controller is a synthesizable HDL core providing a high-speed synchronous serial communication interface. Operation of the controller is similar to that used in the Intel 8XC152 Global Serial

SDLC

Abstract: 3s250E IN SDLC PROTOCOL 80C152 intel 8051 application information xilinx spartan SDLC synchronous signals
Contextual Info: Based on Intel’s 80C152 Global Serial Channel Flexible addressing schemes SDLC Controller Core The SDLC controller is a synthesizable HDL core providing a high-speed synchronous serial communication interface. Operation of the controller is similar to that used in the Intel 8XC152 Global Serial

FTG 1087 S

Abstract: AST 3P, Transmitter
Contextual Info: 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER • 8K Factory Mask Programmable ROM Available ■ Superset of 80C51 Architecture ■ 64KB Data Memory Addressing ■ Multi-Protocol Serial Communication I/O Port 2.048 Mbps/2.4 Mbps Max

80C152

Abstract: 80C152JA
Contextual Info: irrte* 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER • 8K Factory Mask Programmable ROM Available ■ Superset of 80051 Architecture ■ 64KB Data Memory Addressing ■ Multi-Protocol Serial Communication I/O Port 2.048 Mbps/2.4 Mbps Max

80C152JA

Abstract: 80C152 80C152JC 80C51 83C152JA 83C152JC
Contextual Info: i n t o i P W ilL D fifiJD R IÄ lR Y 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER • 8K Factory Mask Programmable ROM Available Superset of 80C51 Architecture ■ 64KB Data Memory Addressing Multi-Protocol Serial Communication

270431

Abstract: 83C152JA
Contextual Info: INTEL CORP UP/PRPHLS 31E D • 4 fiHt:1 7 S Q 0 1 Q Ô 10 b P O a iy K ltM V i n y 7 = 7 ^ -3 7 -0 7 8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ■ 8K Factory Mask Programmable ROM Available ■ ■ ■ ■ m ■ ■ Superset of 80C51 Architecture

intel 8044

Abstract: 270646-008 8XC152JX SDLC 8044 272383 8XC152JA C152 intel DOC 270646 8XC152
Contextual Info: 8XC152JX SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272882-001 The 8XC152JX may contain design defects or errors known as errata. Characterized errata that may cause the 8XC152JX’s behavior to deviate from published specifications are documented in

microtek MICE

Abstract: 80c154 intel ROM 8031 80C154 80C752 microtek 8XC552 HOC154 8031 er 80C552
Contextual Info: EasyPack 8052F M IC R O TE K IN TE R N A TIO N A L INC In-Circuit Emulation and source code debugging support the following microcontrollers families: 8031/32, 8X51/52, 8XC652/654, HOC154, 8344, 80C51FA, 8XC552, 83C752/751/750, 8XC152 and more variants. A member of Microtek's MICE product line for

Intel Microcontroller

Abstract: 80151 microcontroller free of intel 80196 microcontroller 80151 intel 80251 87C51FA 80196 application
Contextual Info: REAL-TIME OPERATING SYSTEMS CMX COMPANY CMX-RTX* • ■ ■ ■ ■ ■ ■ ■ ■ ■ Supports Intel 8051, 80151, 80251 and 80196 Microcontrollers No Royalties on Embedded Code All Source Code Supplied Extremely Fast Context Switch Times Low Interrupt Latency Times

80151

Abstract: 80196 application
Contextual Info: REAL-TIME OPERATING SYSTEMS CMX COMPANY The CMXTracker* • ■ ■ ■ ■ ■ ■ ■ Supports Intel 8051, 80151, 80251, 80196 Microcontrollers Enhances Debugging of Intel Microcontrollers Provides Insight of Application Flow Logging is Captured in Real-Time

task in the processor

Contextual Info: REAL-TIME OPERATING SYSTEMS CMX COMPANY The CMXBug* Debugger • ■ ■ ■ ■ ■ ■ Supports Intel 8051, 80151, 80251 and 80196 Microcontrollers Enhances Debugging of Intel Microcontrollers Provides Insight Into RTOS Task Time Analysis Display RAM and ROM Contents

Contextual Info: DEVELOPMENT SOFTWARE TASKING, INC. TASKING CrossView 51 ROM Monitor Debugger • ■ ■ ■ ■ ■ ■ Code in C, Debug in C Real Windows* Interface Conditional Code and Software Data Breakpoints I/O Simulation Using Files, Timed or Polled Full Trace Including C, Assembler

datasheet transistor said horizontal tt 2222

Abstract: interface of rs232 to UART in VHDL xc9500 80C31 instruction set apple ipad schematic drawing 8 bit alu in vhdl mini project report apple ipad 2 circuit schematic apple ipad Apple iPad 2 panasonic inverter dv 700 manual TT 2222 Horizontal Output Transistor pins out
Contextual Info: Virtex-II Platform FPGA User Guide UG002 v2.2 5 November 2007 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

xilinx vhdl code for floating point square root

Abstract: multiplier accumulator MAC code verilog multi channel UART controller using VHDL 80C31 instruction set vhdl code of 32bit floating point adder verilog code for floating point adder xilinx logicore fifo generator 6.2 xilinx vhdl code for floating point square root o vhdl code for 3-8 decoder using multiplexer vhdl code 32bit LFSR
Contextual Info: R Using the CORE Generator System Introduction This section on the Xilinx CORE Generator System and the Xilinx Intellectual Property IP Core offerings is provided as an overview of products that facilitate the Virtex-II design process. For more detailed and complete information, consult the CORE Generator

4x4 unsigned multiplier VERILOG coding

Abstract: vhdl code for lvds driver 32x32 multiplier verilog code MULT18X18 12v relay interface with cpld in vhdl verilog/verilog code for lvds driver 80C31 instruction set vhdl code for 18x18 unSIGNED MULTIPLIER vhdl pulse interval encoder book national semiconductor
Contextual Info: R Chapter 2 Design Considerations Summary This chapter covers the following topics: • • • • • • • • • • • • • • • • • Rocket I/O Transceiver Processor Block Global Clock Networks Digital Clock Managers DCMs Block SelectRAM Memory

OAOLP2

Abstract: temperature digital display JUMO Lan M smd transistor 1p7 bti ml-2 transistor SMD 1p6 transistor DK qe smd edto 116.4 8052ah basic toba 639 270645
Contextual Info: MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994 Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein.

87C196KN

Abstract: intel embedded microcontroller handbook 8XC196KC Users manual 87C196KD Users manual MCS51 Manual 87C196KD20 8XC196KC Users Guide 8XC196KD users manual 87C196MH MCS-96 Users guide
Contextual Info: ZapCode II Handbook A Guide to Electronic ROM-code Transmittal ZapCode II Handbook December 1995 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of

AVC51

Abstract: avocet compiler avocet manual Union Microsystems
Contextual Info: DEVELOPMENT SOFTWARE AVOCET SYSTEMS, INC. AVC51 ANSI C Compiler • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete ANSI C Global, Peephole, Stack and Jump Optimizations High-Level Compatible With All Major ICEs Support Bank Switching Includes Library Source Code