8192X8192 Search Results

ST-BUS

Abstract: Mode-S 512x512
Contextual Info: TSI Family Products Selector Guide  Par t Number s IDT72V71660 Switching Capacity 16384x16384 I/O Data Str eams 64 Bit Rates Mb/s 2,4,8,16 IDT72V73260 16384x16384 32 IDT72V71650 8192x8192 IDT72V73250 Bus For mats ST-BUS, GCI Supply Voltage 3.3V Available Packages

Sony IMX 183

Abstract: Sony sony cmos sensor imx 178 Sony imx 214 Sony ImX 252 sony cmos sensor imx 226 Sony IMX 219 CMOS Sony "IMX 219" CMOS sony IMX 322 cmos sony cmos sensor imx 185
Contextual Info: i.MX 6Solo/6DualLite Applications Processor Reference Manual Document Number: IMX6SDLRM Rev. 1, 04/2013 i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 1, 04/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1

PM965

Contextual Info: Mobile Intel 965 Express Chipset Family Datasheet Revision 001 May 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

iNAND eMMC 4 41

Abstract: rk3066 ARGB888
Contextual Info: RK3066 Datasheet brief Rev1.0 RK3066 Datasheet brief Revision 1.0 Feb. 2012 Rockchips Confidential 1 RK3066 Datasheet brief Rev1.0 Revision History Date Revision Description 2011-10-30 0.0 Initial Release 2012-02-15 1.0 Add package information Rockchips Confidential

cortex a7

Abstract: 88PM812 88W8777
Contextual Info: Marvell PXA1088 Quad-Core WCDMA/TD-SCDMA Communication Processor Quad-Cortex A7, High-Performance, Low-Power, Low-Cost PRODUCT OVERVIEW The Marvell PXA1088 is a highly integrated quad-core application and communications mobile System-on-Chip SoC that provides high-performance, low-power mobile computing; support for all global broadband 3G standards, enabling seamless

rk3188

Abstract: RK3188-T ARGB888 emmc boot sequence
Contextual Info: RK3188Technical Reference ManualRev 1.2 Chapter 1 Introduction RK3188 is a low power, high performance processor for mobile phones, personal mobile internet device and other digital multimedia applications, and integrates quad-core Cortex-A9 with separately NEONand FPU coprocessor.

Contextual Info: Marvell PXA1088 Quad-Core WCDMA/TD-SCDMA Communication Processor Quad-Cortex A7, High-Performance, Low-Power, Low-Cost PRODUCT OVERVIEW The Marvell PXA1088 is a highly integrated quad-core application and communications mobile System-on-Chip SoC that provides high-performance, low-power mobile computing; support for all global broadband 3G standards, enabling seamless

PL-1061

Abstract: PQFP256 LQFP216 24bit 2654 uclinux R3000 Prolific usb uart Prolific Technology pl1061
Contextual Info: PL-1061 Open Architecture for Photo Viewer Applications OVERVIEW The PL-1061 is a low-cost high-performance single chip mobile computing system solution. With a powerful 32-bit RISC CPU core and a wide range of hardware controlled peripheral interfaces, it is capable of

TW2880

Abstract: TW2864
Contextual Info: Techwell Application Note 1659 TW2880P-BC2-GR Chip Application Note Table of Contents Section 1: Clockgen and PLL . 11

Mali-400

Contextual Info: Allwinner Technology CO., Ltd. A13 User Manual V1.2 2013.01.08 A13 Allwinner Technology CO., Ltd. A13 Revision History Version Date Author V1.0 2012.04.16 Initial version V1.1 2012.10.25 Modify SDRAM/NAND module descriptions V1.2 2013.1.8 A13 User Manual V1.2

H.264 encoder cortex a8

Abstract: arm cortex a9 cortex-a9 CMOS Sensor 1080p H.264 60 android mobile MOTHERBOARD CIRCUIT diagram 667 transistor ecb CHINA TV uoc ARm cortexA9 GPIO android mobile circuit diagram "ARM Cortex A9"
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

arm cortex a9

Abstract: H.264 encoder cortex a8 "ARM Cortex A9" cmos digital camera module MMC 4.2 "NOR Flash controller" H.264 codec PD46 Dual-core ARM Cortex-A9 CPU cortex-a9
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − production data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

arm cortex a9

Abstract: RMII PHY H.264 codec rgb led 16X32 encoder h.264 CMOS Sensor 1080p H.264 60 Tablets DIAGRAM SPEAR13 how to flash an android media "ARM Cortex A9"
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP