8-BIT PARALLEL/SERIAL TRANSCEIVER Search Results

Contextual Info: nPower BBT3420 Quad Multi-rate Transceiver Data Sheet August, 2002 4 Channel Multi-rate Transceiver for Backplane Applications FN7481 Applications The nPower BBT3420 is a quad 8-bit/10-bit parallel-to-serial and serial-to-parallel transceiver device ideal for high

Contextual Info: 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 01 — 29 May 2007 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks.

74LVC595A

Abstract: 74LVC595ABQ 74LVC595AD 74LVC595APW DHVQFN16 TSSOP16
Contextual Info: 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 01 — 29 May 2007 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks.

c3355

Abstract: transistor c3355 CXB1563Q CXB1590Q QFP080-P-1414 r315k 1/transistor c3355
Contextual Info: CXB1590Q SDH 8 bit 622 Mbps Transceiver Description The CXB1590Q is a transceiver IC with built-in PLL for ATM network. For a receiver 622 Mbps serial data is received and output it as the 8-bit parallel data; for a transmitter 622 Mbps 8-bit parallel data is

C3355

Abstract: CXB1563Q CXB1590Q
Contextual Info: SONY CXB1590Q SDH 8 bit 622 Mbps Transceiver Description The CXB1590Q is a transceiver IC with built-in PLL for ATM network. For a receiver 622 Mbps serial data is received and output it as the 8-bit parallel data; for a transmitter 622 Mbps 8-bit parallel data is

Contextual Info: SONY CXB1590Q SDH 8 bit 622 Mbps Transceiver Description The CXB1590Q is a transceiver IC with built-in PLL for ATM network. For a receiver 622 Mbps serial data is received and output it as the 8-bit parallel data; for a transmitter 622 Mbps 8-bit parallel data is

d13d1

Abstract: 16P2N M62320P
Contextual Info: MITSUBISHI < STD. LINEAR ICs > M62320P,FP 2 8-BIT I/O EXPANDER for I C BUS GENERAL DESCRIPTION The M62320P/FP is a CMOS 8-bit I/O expander which has serial to parallel and parallel to serial data converting functions. It can communicate with a microcontroller via few wiring

S1217

Abstract: 8-bit parallel/serial transceiver SDH -209
Contextual Info: S1217 Serial OC-3/12 - to - 8 Bit Transceiver P RODUCT BR IE F The S1217 transceiver provides a fully integrated serialization/de-serialization device that performs all necessary parallel-to-serial and serial-to-parallel functions in conformance with SONET/SDH transmission standards. The S1217 receive

Contextual Info: M62320P/FP 8-bit I/O Expander for I2C BUS REJ03D0863-0201 Rev.2.01 Dec 27, 2007 Description The M62320P/FP is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial data converting functions. It can communicate with a microcontroller via few wiring thanks to the adoption of the two-line I2C BUS.

Contextual Info: M62320P/FP 8-bit I/O Expander for I2C BUS REJ03D0863-0200 Rev.2.00 Dec 15, 2006 Description The M62320P/FP is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial data converting functions. It can communicate with a microcontroller via few wiring thanks to the adoption of the two-line I2C BUS.

S1213

Contextual Info: S1213 Quad Serial OC-3/12 - to - 8 Bit Transceiver P RODUCT BR IE F The S1213 device provides fully integrated serialization/de-serialization capabilities for Quad Transceiver. The device performs all necessary parallel-to-serial and serial-to-parallel functions in conformance with SONET/SDH transmission standards. The standard operating range is 155.52 Mbps or 622.08 Mbps.

Contextual Info: SONY CXB 1 5 8 6 AR 10 Bit 1.0625 Gbaud Transceiver Description The CXB1586AR is a transceiver IC with a built-in PLL fo r Fibre C hannel. For a re ce ive r 1.0625 Gbaud serial data is received and output it as the 10-bit parallel data; for transmitter 1.0625 Gbaud 10bit parallel data is output as the serial data.

verilog prbs generator

Abstract: BBT3400 MDIO MDC nPowerBBT3400
Contextual Info: nPower BBT3400 Quad 3.125G Transceiver XAUI to XGMII Low Power CMOS 4 Channel 3.125Gbps Transceiver Features • • • • • • • • • • • • • • • • Applications The nPower BBT3400 is a quad 8-bit/10-bit parallelto-serial and serial-to-parallel transceiver device ideal

T7250

Abstract: 54-423 hdlc t725 T7250C
Contextual Info: Product Brief April 1998 T7250 S/T-Interface with HDLC Features Description • TE mode S/T-interface ■ D-channel HDLC controller ■ Automatic D-channel contention resolution ■ Two serial TDM interfaces compatible with variable bit-rate codecs ■ 8-bit parallel control interface

10-001

Abstract: sae j1850 J1850 MC68HC56FN MC68HC57FN J1850 TRANSIENT PROTECTION sae j1850 vpw
Contextual Info: JUN 2 v 'Ml Order this document by BR784/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C68HC56/57 Technical Summary 8-Bit Data Link Controller Introduction The MC68HC56/57 Data Link Controller Parallel/Serial DLCP/S handles microcontroller unit (MCU) to Society of Automotive Engineers (SAE) J1850 bus interface duties. These integrated

USBN9602-28M

Abstract: COP888EG CRC16 M28B USBN9602
Contextual Info: USBN9602 Universal Serial Bus Full Speed Function Controller With DMA Support 1.0 General Description Block Diagram CS RD WR trol endpoint EP0 and six FIFOs for an additional six unidirectional Endpoint Pipes to support USB interrupt, bulk and isochronous data transfers. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU

k241

Contextual Info: 3. Custom Mode SGX52003-1.2 Introduction The Custom mode of the Stratix GX device includes the following features: • ■ ■ ■ ■ Serial data rate range from 500 Mbps to 3.1875 Gbps Input reference clock range from 25 to 650 MHz Parallel interface width of 8, 10, 16, or 20-bit support

Contextual Info: 000 BUS-6410011 ILC DATA DEVICE CORPORATION_ MIL-STD-1553 TERMINAL BIT PROCESSOR FEA TURES • 16 B IT OR 8 B IT BYTE PARALLEL OR SERIAL I/O D E S C R IP T IO N The DDC BUS-6410011 is a term inal B it Processor, w hich consists o f a Man­ chester II Converter and a DDC

prbs generator

Abstract: STM-16 LIU 4X CMU clock mhz XRT91L82
Contextual Info: JUNE 2007 REV - 1.0.0 Network and Transmission XRT91L82 Datasheet NOTES: II XRT91L82 REV - 1.0.0 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE OF CONTENTS TABLE OF CONTENTS . III

Contextual Info: FC106 Fibre Channel Transceiver 1.0625 GBaud FEATURES • Serial Link Transceiver Parallel Interface • serializer and deserializer • implementing the Fibre Channel FCO and FC1 layers ■ Direct support for 1.0625 GBaud Fibre Channel ANSI X3.230-1994 rates

prbs pattern generator

Abstract: prbs generator GR-253 STM-16 STS-48 XRT91L82
Contextual Info: xr XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER APRIL 2005 REV. P1.0.5 GENERAL DESCRIPTION of the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status

M27218-22

Abstract: M27218 27218-DSH-001-E LVDS 31 pin AA10 mindspeed command M2721822
Contextual Info: M27218 Octal Backplane Transceiver Data Sheet May 2006 27218-DSH-001-E 2004, 2005, 2006 Mindspeed TechnologiesTM, Inc. All rights reserved. Information in this document is provided in connection with Mindspeed TechnologiesTM "MindspeedTM" products. These materials are provided by Mindspeed as a service to its customers and may be used for

am transmitter circuit diagram and hw to make it

Abstract: STM-16 XRT91L80 XRT91L80IB tms fifo 4bit
Contextual Info: xr XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER MARCH 2005 REV. P1.0.4 GENERAL DESCRIPTION AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET

1000kA

Abstract: block diagram of automatic flush system 0X00H
Contextual Info: áç PRELIMINARY XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER DECEMBER 2003 REV. P1.0.2 GENERAL DESCRIPTION an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip