7C373I Search Results

Contextual Info: 7C373i: October 14, 1995 Revision: ADVANCED INFORMATION 7C373i UltraLogict 64ĆMacrocell Flash CPLD FLASH370it family of highĆdensity, highĆ speed CPLDs. Like all members of the FLASH370i family, the 7C373i is deĆ signed to bring the ease of use and high

Contextual Info: 7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable™ ISR™ Flash technology — JTAG interface

Contextual Info: fax id: 6138 1CY 7C37 3i 7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS 7C373i UltraLogic 64-Macrocell Flash CPLD Features • Available in 84-pin PLCC and 100-pin TQFP packages • Pin compatible with the CY7C374i • 64 macrocells in four logic blocks • 64 I/O pins Functional Description

Contextual Info: fax id: 6138 7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

L0523

Abstract: 236s2 319H
Contextual Info: CY7C373Ì UltraLogic 64-Macrocell Flash CPLD ADVANCED INFORMATION Features FuvsH370i'M family of high-density, high­ speed CPLDs. Like all m em bers of the • 64 m acrocells in four logic blocks FLASn370i family, the 7C373i is de­ • 64 I/O pins signed to bring the ease of use and high

Contextual Info: 7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface • Bus Hold capabilities on all I/Os and dedicated inputs

preset resistor

Contextual Info: fax id: 6138 7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: fax id: 6447 Back Using Cypress CPLDs in Mixed-Voltage Systems Introduction Table 1. VCCINT and VCCIO for FLASH370i Improvements in process technologies provide better densities, increased performance and lower power consumption in programmable logic devices. As device dimensions are reduced, the voltage that the transistors can withstand also decreases. The increasing demand for lower system power consumption has brought many new design challenges. Among

Contextual Info: CY7C373Ì ADVANCED INFORMATION m r CYPRESS UltraLogic 64-Macrocell Flash CPLD Features FLASH370i™ family o f high-density, high­ • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR

ULTRA37000TM

Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS 7C373i UltraLogic 64-Macrocell Flash CPLD Features • Available in 84-pin PLCC and 100-pin TQFP packages • Pin compatible with the CY7C374i • 64 macrocells in four logic blocks • 64 I/O pins Functional Description

Contextual Info: fax id: 6447 Using Cypress CPLDs in Mixed-Voltage Systems Introduction Table 1. VCCINT and VCCIO for FLASH370i Improvements in process technologies provide better densities, increased performance and lower power consumption in programmable logic devices. As device dimensions are reduced, the voltage that the transistors can withstand also decreases. The increasing demand for lower system power consumption has brought many new design challenges. Among

Contextual Info: 73i 7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable™ ISR™ Flash technology — JTAG interface

7C375i

Abstract: 37000V
Contextual Info: Using Cypress CPLDs in Mixed-Voltage Systems Introduction Table 1. VCCINT and VCCIO for FLASH370i Improvements in process technologies provide better densities, increased performance and lower power consumption in programmable logic devices. As device dimensions are reduced, the voltage that the transistors can withstand also decreases. The increasing demand for lower system power consumption has brought many new design challenges. Among