7C1302V25 Search Results

7C1302V25 Price and Stock

Filter by Manufacturer

Cypress Semiconductor


Cypress Semiconductor CY7C1302V25-133BZC SRAM Chip Sync Dual 2.5V 9M-bit 512K x 18 3ns 165-Pin FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Bristol Electronics	CY7C1302V25-133BZC		20		1	1 $54.00 10 $49.68 100 $49.68 1000 $49.68 10000 $49.68	Buy Now

7C1302V25 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1302V25 Abstract: CY7C1302V25-133BZC Contextual Info: yy 7c1302V25: Rev 1.0 Revised: February 15, 2000 7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth	Original	7c1302v25 cy7c1302v25 167-mhz cy7c1302v25-133bzc	PDF
Contextual Info: 7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	cy7c1302v25 167-mhz	PDF
2L60 Abstract: SAMSUNG os application note 3N62 CY7C1302V25 Contextual Info: 7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent read and write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5-ns clock-to-valid access time • Two-word burst on all accesses	Original	cy7c1302v25 167-mhz 2l60 samsung os application note +13n62	PDF
CY7C1302V25 Abstract: 6n38 11x15 Contextual Info: 7C1302V25 ADVANCE INFORMATION 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	cy7c1302v25 167-mhz 6n38 11x15	PDF
CY7C1302V25 Contextual Info: yy 7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time	Original	cy7c1302v25 167-mhz	PDF
CY7C1302V25 Abstract: CY7C1302V25-167 Contextual Info: 7C1302V25 ADVANCE INFORMATION 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	cy7c1302v25 167-mhz cy7c1302v25-167	PDF