777777T Search Results

Contextual Info: HM66205 S e rie s-524,288-Word x 8-Bit High Density CM O S Static RAM Module • PIN ARRANGEMENT Description The HM66205 is a high density 4M-bit static RAM module consisting of 4 pieces HM628128LTS products TSOP type 1M static RAM and a HD74ACT138FP equivalent product (SOP

TC55V4376FF

Abstract: TC55V4376FF-100
Contextual Info: TO SH IBA TC55V4376FF-100,-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 36-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4376FF is a 4,718,592-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 36 bits. It is designed for use as a secondary cache to support microprocessor

Contextual Info: TOSHIBA TC55V4336FFI-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 32-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4336FFI is a 4,194,304-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 32 bits. It is designed for use as a secondary cache to support microprocessor

Contextual Info: TO SH IBA TC55V4376FF-100,-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 36-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4376FF is a 4,718,592-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 36 bits. It is designed for use as a secondary cache to support microprocessor

tney2

Abstract: HM5241 5241605
Contextual Info: HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605 is offered in 2 banks for improved performance. _ F e a tu re s •3.3V Power s u p p

pin diagram 7400 series

Abstract: CI 7474 hs 111-0 7400 fan-out 74164 TTL CI 7400 7474 pin out diagram CI 7400 ttl 74164 HS5212
Contextual Info: Hybrid Systems W W CORPORATION HS 5210 Series 12-Bit Adjustment Free ADCs FEATURES • 12-Bit Conversion in 10 m s , Typical; 13 \x s, Maximum ■ Adjustment-Free, ±0.0125% Linearity ■ Low Power.670 mW, Typical ■ Wide Operating Temperature Range.

KM658128

Contextual Info: m s« KM658128 SAMSUNG Semiconductor 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM May 1991 FEATURES DESCRIPTION • Fast Access Time: — CE Access Tim e. 80, 100, 120ns Max — Cycle Time Random Read/Write Cycle Time .130, 160, 190ns (Max)

Contextual Info: MN5240 ^ MICRO NETWORKS 10 and 12-Bit HIGH-SPEED CONVERTERS DESCRIPTION FEATURES • Fast Conversion Times: 5ftsec Max for 12 Bits 4.2/xsec Max for 10 Bits • Complete A/D Function: Internal Clock Internal Reference Input Buffer Short-Cycle Pin • No Clock Adjusting

Contextual Info: ADC87 mrnm Micro Networks 12-Bit, 8/isec MILITARY A /D C O N V E R T E R a DIVISION O f U N tT M O O « CORPORATION DESCRIPTION FEATURES • Fully Guaranteed -55°C to +125°C Operation • 8/isec Max Conversion Time • Complete/Versatile A/D Function: Internal or External Clock

multiturn preset potentiometer

Contextual Info: MN5240 10 an d 12-Bit H IG H -S P E E D A /D C O N V E R T E R S MICRO NETWORKS DESCRIPTION • Fast Conversion Times: 5/iSec Max for 12 Bits 4.2/^sec Max for 10 Bits • Complete A/D Function: Internal Clock Internal Reference Input Buffer Short-Cycle Pin

TC55V4376FFI-83

Contextual Info: TO SH IBA TC55V4376FFI-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 36-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4376FFI is a 4,718,592-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 36 bits. It is designed for use as a secondary cache to support microprocessor

TC55V4336FFI-83

Abstract: 032J
Contextual Info: TOSHIBA TC55V4336FFI-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 32-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4336FFI is a 4,194,304-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 32 bits. It is designed for use as a secondary cache to support microprocessor

Contextual Info: HM62V8128 Series 131072-Word X Product Preview 8-Bit High Speed CMOS Static RAM D escription O rd e rin g In fo rm atio n The H itachi H M 62V 8128 is a CM OS static RAM organized 128 kw ord X 8 bit. It realizes h ig h e r d en sity , h ig h e r p erfo rm a n ce and low

Contextual Info: HM534253 S eries-262,144-Word x 4-Bit Multiport CMOS Video RAM • DESCRIPTION HM 534253JP Series The HM534253 is a 1-Mbit multiport video RAM equipped with a 256k-word x 4-bit dynamic RAM and a 512-word x 4-bit SAM serial access memory . Its RAM

Contextual Info: TO SH IBA TC55V4336FF-100,-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 32-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4336FF is a 4,194,304-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 32 bits. It is designed for use as a secondary cache to support microprocessor

Contextual Info: II MN5210 Series [I mb 13jisec, 12-Bit M ILITA R Y AID C O N V E R T E R S MICRO NETWORKS DESCRIPTION • 13/isec Maximum Conversion Time • +1/2LSB Linearity and No Missing Codes Guaranteed Over Temperature • Small 24-Pin DIP • +1LSB Zero Error • +2LSB Absolute Accuracy

CL2C12

Contextual Info: MOSEL- VITELIC V53C100N HIGH PERFORMANCE, 3.3 VOLT 1 M X 1 B IT FA ST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C100N 60/60L PRELIMINARY 70/70L 80/80L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA) 35 ns 40 ns 45 ns

mcm2018

Abstract: mcm2018a
Contextual Info: MOTOROLA S E M IC O N D U C T O R TECHNICAL DATA MCM2018A F a st 1 6 K B it S ta tic R A M The M C M 2 0 1 8 A is a 16,384 bit static random access memory organized as 2048 w ords by 8 bits, fabricated using Motorola's high-performance silicon-gate M O S {H M O S I technology. It uses an innovative design approach which combines the

8 x 8 LED Dot Matrix 8086 assembly language code

Abstract: 5 x 7 LED Dot Matrix 8086 assembly language code interfacing STEPPER MOTOR with 8086 microprocessor 8085 MICROCOMPUTER SYSTEMS USERS MANUAL stepper motor interface with 8086 block diagram 8086 microprocessor mini project circuit Interfacing of 16k EPROM and 8K RAM with 8085 AmSYS29 Interfacing of 32k ram and 16K EPROM with 8085 str f 6264
Contextual Info: MULTIBUS OEM Products and Microprogrammable Development Tools E lectron ic C om ponents Instru m e n ta tion and C om puter Systems 5th Floor, Randover House, Dover Street, R andburg. South Africa. s i P.O. Box 56420. Pinegow rie 2123. South Africa. 011 789-2400 (5 lines).

HM534251

Abstract: HM534251-10 HM534251ZP-10 HM534251ZP-12 HM534251ZP HM534251JP-15 HM534251-15 LB203 DC HM534251JP-10 72FL
Contextual Info: H I TA C H I / L O C I C / A R R A Y S / M E M SIE D M M 1 b 5G 3 0 0 n 3 1 5 flfl^ • H I T S HM534251 S e rie s-262,144 x 4-Bit Multiport CMOS Video Random Access Memory ■ DESCRIPTION HM534251JP Series The HM534251 is a 1-Mbit multiport video RAM equipped with a 256k-word x

Contextual Info: ADVANCED ANALOG A Division of intech ADC5610 SERIES DESCRIPTION HIGH SPEED 12-BIT A /D CONVERTERS The ADC5610 Series devices are successive approximation 12-bit A/D converters with 13/iSec conversion time. These devices are laser trimmed for ultra accuracy and reliability and require no

TC55V4336FF

Abstract: TC55V4336FF-100
Contextual Info: TO SH IBA TC55V4336FF-100,-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 32-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4336FF is a 4,194,304-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 32 bits. It is designed for use as a secondary cache to support microprocessor

LA 8512

Contextual Info: y ADC84 ADC85 H IG H -S P E E D , 1 2 -B it MICRO NETWORKS A /D C O N V E R T E R S D E S C R IP TIO N • Fast Conversion Times: 8fisec max. for 12 Bits 5^sec max. for 10 Bits • ± 1/ 2 LSB Linearity and No M issing Codes G uaranteed Over Tem perature • Complete:

83ADV

Contextual Info: TO SH IBA TC55V4376FFI-83 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 36-BIT SYNCHRONOUS FLOW THROUGH STATIC RAM DESCRIPTION The TC55V4376FFI is a 4,718,592-bit synchronous Flow through static random access memory SRAM organized as 131,072 words by 36 bits. It is designed for use as a secondary cache to support microprocessor