75285 Search Results

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

SN74HC74

Contextual Info: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO

JFET 4405

Abstract: tle20641
Contextual Info: TLE2064M, TLE2064AM EXCALIBUR JFET-INPUT HIGH-OUTPUT-DRIVE UPOWER QUAD OPERATIONAL AMPLIFIERS D3367, N O V EM B ER 1989 - R E V IS E D O C T O B E R 1991 available features Excellent Output Drive Capability V 0 = ± 2.5 V Min at R L = 100 £2, VCC± = ± 5 V

bd 9d

Abstract: SN74ALS29841
Contextual Info: SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS S D A S 1 4 9 A - JU N E 1 9 8 8 - REVISED JA N U A R Y 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly DW OR NT PACKAGE TOP VIEW Bus-Structured Pinout m Provides Extra Bus-Driving Latches

MXBL

Abstract: SN7517
Contextual Info: Ôci b l 7 5 4 QGñ5bñ3 "T -^5-4 5 - 0 ^ 4 • T II4 S N 75 174 QUADRUPLE DIFFERENTIAL LINE DRIVER H INSTR LIN /IN TFC 4DE D 02601, OCTOBER 1980-REVISED MAY 1988 J OR N PACKAGE » Meets EIA Standards RS-422-A and RS-485 and CCITT Recommendations V.11 and

Contextual Info: TEXAS INSTR -C LI N/I NTFO *ìl 8961724 TEXAS INSTR LIN /IN TFC dË J 5 ^ 1 7 2 4 007 5115 2 91D ADVANCE INFORMATION 75912 SN7S609 DUAL FLUX-REGULATING ACTUATOR T -5 2 -1 3 -4 5 2.6-A Current Capability per Channel K V SINGLE-IN-LINE PACKAGE (TOP VIEW)

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

CT 2048

Abstract: D8228
Contextual Info: SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L 2048 x 9,4096 x 9,8192 x 9,16384 x9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 Reads and Writes Can Be Asynchronous or Coincident Organization: - SN74ACT7203L - 2048 x 9

Contextual Info: SN54LVU04, SN74LVU04 HEX INVERTERS S C L S 1 B 5 B - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

SN74LVCC4245

Contextual Info: SN74LVCC4245 OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS _ SCAS584A - NOVEMBER 1696 - REVISED JANUARY 1997 EPICrM Enhanced-Performance Implanted CMOS Submicron Process DB, DW, OR PW PACKAGE

Contextual Info: SN74LVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCAS279B-JANUARY 1993 - REVISED JULY 1995 I • EP/C Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MII-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN55563A, SN55564A ELECTROLUMINESCENT ROW DRIVERS D 3 3 1 3 , OCTOBER 1 9 8 9 S N 55S63A . . . FJ PACKAGE • Each Device Drives 34 Electrodes • Selectable Open-Source or Open-Drain Output • Outputs Rated at 225 V • Output Current Capability: - 9 0 mA to 150 mA

Contextual Info: SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069S- NOVEMBER 198« - REVISED MARCH 1996 • ■ I • • Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers I I •

8 channel remote control transmitter circuit

Abstract: 8 channel rf remote control remote control Pulse Position Modulation circuit SN75605
Contextual Info: PRE!.I!1IÎ!AnY APRIL 1980 ADVANCED CIRCUITS SN76605N REMOTE CONTROL TRANSMITTER CHlAb 002926 • Low Icc due to I*L technology. ] 16 MODULATION SWITCH TIMING CURRENT CONTROL 2[ ] 15 EXTERNAL MODULATION CHI ON/OFF CONTROL 3[ 3w RF VCC CH2 ON/OFF CONTROL •»[

TL751M10

Contextual Info: TL750M, TL751M SERIES LOW-DROPOUT VOLTAGE REGULATORS SLVS021D - JA N U A R Y 1986 - REVISED A U G U S T 1996 • 60-V Load-Dump Protection • Very Low Dropout Voltage, Less Than 0.6 V at 750 nr A • Overvoltage Protection • Internal Thermal Overload Protection

sn74als662

Abstract: sn74als663 sn74als662a SN74ALS853 2114D
Contextual Info: SN54ALS652, SN54A LS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SDAS066E - DECEMBER 1983 - REVISED JANUARY 1995 Bus Transceivers/Registers Independent Registers and Enables for

Contextual Info: SN54AHCU04, SN74AHCU04 HEX INVERTERS SCLS234A - OCTOBER 1995 - REVISED MARCH 1996 SN54AHCU04 . . . J OR W PACKAGE SN74AHCU04. . . D, DB, N OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V V^c EPIC (Enhanced-Performance Implanted CMOS) Process Unbuffered Outputs

ALS804A

Abstract: 74ALS804 cc196 74AS804
Contextual Info: SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C - DECEMBER 1982- REVISED JANUARY 1995 • High Capacltive-Drlve Capability • ALS804A Has Typical Delay Time of 4 ns Cj. = 50 pF and Typical Power Dissipation of 3.4 mW Per Gate

74HC269

Contextual Info: SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134A - DECEMBER 1982 - REVISED JANUARY 1996 8-Blt Parallel-Out Storage Register Performs Serlal-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable Input Simplifies Expansion

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

Pulse-Width-Modulation Control Circuit

Abstract: D372
Contextual Info: TL598M PULSE-WIDTH-MODULATION CONTROL CIRCUIT _ D3726, APRIL 1991-HEVISED SEPTEMBER 1991 J PACKAGE TOP VIEW Complete PWM Power Control Function Totem-Pole Outputs for 200-mA Sink or Source Current J ERROR IN + [ AMP1 < ^ lN_ t

Contextual Info: TPS7133QPWP, TPS7133Y MICROPOWER LOW-DROPOUT LDO VOLTAGE REGULATORS SLVS101A - FEBRUARY 1995 - REVISED AUGUST 1995 • Thermally Enhanced Surface-Mount Package (PWP) • High-Current (500-mA) LDO Regulator • Very Low-Dropout Voltage. . . Maximum of 60 mV at Iq s 100 mA