74LVC1G Search Results

Contextual Info: 74LVC1G14 Single Schmitt-trigger inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free

application note tssop5 nxp

Contextual Info: 74LVC1G06 Inverter with open-drain output Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

marking VU SOT363

Contextual Info: 74LVC1G11 Single 3-input AND gate Rev. 7 — 4 July 2012 Product data sheet 1. General description The 74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

74LVC1G53

Abstract: 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8
Contextual Info: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 — 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select

74LVC1G3157GV

Abstract: 74LVC1G3157GW 74LVC1G3157 74LVC1G3157GF 74LVC1G3157GM JESD22-A114E
Contextual Info: 74LVC1G3157 2-channel analog multiplexer/demultiplexer Rev. 02 — 18 September 2007 Product data sheet 1. General description The 74LVC1G3157 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select

74LVC1G04

Abstract: 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW JESD22-A114E MO-203
Contextual Info: 74LVC1G04 Single inverter Rev. 08 — 27 April 2009 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

74LVC1G06

Abstract: 74LVC1G06GF 74LVC1G06GM 74LVC1G06GV 74LVC1G06GW JESD22-A114E
Contextual Info: 74LVC1G06 Inverter with open-drain output Rev. 07 — 12 July 2007 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

74LVC1G58

Abstract: 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW JESD22-A114E marking code 5
Contextual Info: 74LVC1G58 Low-power configurable multiple function gate Rev. 04 — 27 April 2009 Product data sheet 1. General description The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

74LVC1G74DC

Abstract: 74LVC1G74 74LVC1G74DP 74LVC1G74GD 74LVC1G74GM 74LVC1G74GT
Contextual Info: 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 9 — 5 August 2010 Product data sheet 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

74LVC1G332

Abstract: 74LVC1G332GF 74LVC1G332GM 74LVC1G332GV 74LVC1G332GW
Contextual Info: 74LVC1G332 Single 3-input OR gate Rev. 3 — 26 October 2010 Product data sheet 1. General description The 74LVC1G332 provides one 3-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

74LVC1G126

Abstract: 74LVC1G126GF 74LVC1G126GM 74LVC1G126GV 74LVC1G126GW
Contextual Info: 74LVC1G126 Bus buffer/line driver; 3-state Rev. 9 — 25 August 2010 Product data sheet 1. General description The 74LVC1G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A LOW-level at pin OE

74LVC1G125GW

Abstract: 74LVC1G125 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV VM MARKING CODE SOT353
Contextual Info: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 8 — 24 August 2010 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE

74LVC1G157

Abstract: 74LVC1G157GF 74LVC1G157GM 74LVC1G157GV 74LVC1G157GW
Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 4 — 28 October 2010 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data

Contextual Info: 74LVC1G19 1-of-2 decoder/demultiplexer Rev. 7 — 10 September 2014 Product data sheet 1. General description The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y true and 2Y

74LVC1G157GW

Abstract: 74LVC1G157GV 74LVC1G157 74LVC1G157GM
Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 01 — 25 April 2005 Product data sheet 1. General description The 74LVC1G157 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

Contextual Info: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 02 — 10 April 2006 Product data sheet 1. General description The 74LVC1G53 is a high-performance, low-power, low-voltage, Si-gate CMOS device that provides superior performance to most advanced CMOS compatible TTL families.

74LVC1G86

Abstract: 74LVC1G86GM 74LVC1G86GV 74LVC1G86GW
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC1G86 2-input EXCLUSIVE-OR gate Product specification Supersedes data of 2002 Nov 15 2004 Sep 08 Philips Semiconductors Product specification 2-input EXCLUSIVE-OR gate 74LVC1G86 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V

74LVC1G86

Abstract: 74LVC1G86GW
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC1G86 2-input EXCLUSIVE-OR gate Preliminary specification Supersedes data of 2000 Dec 22 File under Integrated Circuits, IC24 2001 Apr 06 Philips Semiconductors Preliminary specification 2-input EXCLUSIVE-OR gate 74LVC1G86

74LVC1G04

Abstract: 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW
Contextual Info: 74LVC1G04 Single inverter Rev. 9 — 26 October 2010 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

74LVC1G384

Abstract: 74LVC1G384GF 74LVC1G384GM 74LVC1G384GV 74LVC1G384GW
Contextual Info: 74LVC1G384 Bilateral switch Rev. 3 — 3 November 2010 Product data sheet 1. General description The 74LVC1G384 provides one single pole, single throw analog switch function. It has two input/output terminals Y and Z and an active LOW enable input pin (E). When pin E

74LVC1G10

Abstract: 74LVC1G10GF 74LVC1G10GM 74LVC1G10GV 74LVC1G10GW
Contextual Info: 74LVC1G10 Single 3-input NAND gate Rev. 2 — 21 October 2010 Product data sheet 1. General description The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74LVC1G58

Abstract: 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW
Contextual Info: 74LVC1G58 Low-power configurable multiple function gate Rev. 05 — 15 October 2010 Product data sheet 1. General description The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,