74LS138 3 TO 8 DECODER PIN DESCRIPTION Search Results

and gate 74LS138

Abstract: SP74HCT138N TTL 74ls138 74LS138 LOGIC OF 74LS138 pin for 74LS138 74LS138 pin configuration SP74HCT138 SP74HCT138J 74LS138 pin
Contextual Info: SPI •jri- SP74HCT138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B ■ Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CM OS technology

l381

Abstract: and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
Contextual Info: y SP74SC138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B • Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CMOS technology ■ Full TTL interface capability

Ic 74hc138 logic diagram

Contextual Info: Revised February 1999 S E M IC Q N D U C T O R T M MM74HC138 3-to-8 Line Decoder The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to V qq and ground.

74LS138

Abstract: 74LS138 3 to 8 decoder Pin 74LS138 pin diagram ls138 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
Contextual Info: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32

LOGIC OF 74LS138

Abstract: 74LS138 3 to 8 decoder notes 74LS138 pin configuration 74LS138 pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
Contextual Info: Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 TYPICAL PROPAGATION

pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function 74LS138 LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
Contextual Info: 74LS138, S138 Signetics Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 74LS138

74ls138 truth table

Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
Contextual Info: g MOTOROLA SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex­

74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note 74ls138 LS138 Motorola
Contextual Info: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32

LOGIC OF 74LS138

Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin
Contextual Info: 74LS138, S138 Signetics Decoders/Dem ultiplexers 1-Of-8 D e co d e r/D e m u ltip le xe r Product Specification L o g ic P rod ucts FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding

74LS138 pins

Abstract: 02830
Contextual Info: Revised February 1999 MM74HCT138 3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits feature high noise immunity and low power consumption usually

CI 74LS138

Abstract: 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74LS138 ttl
Contextual Info: Signelics 74LS138, S138 Decoders/Demultiplexers 1 -O f - 8 D e c o d e r /D e m u ltip le x e r Product Specification L o g ic P ro d u c ts FEATURES • Demultiplexing capability • Multiple input enable fo r easy expansion TYPE 74LS138 74S138 • Ideal fo r m em ory chip select

Contextual Info: Am25LS138 • Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M • Inverting and non-inverting enable inputs • A m 2 5 L S devices offer the following improvements over Am 54/74LS

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception Schottky Clamped for High Performance

M02S7S7

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception • Schottky Clamped for High Performance

SN54138

Abstract: SN74LS138 LS138 SN54LS138 SN54S138 SN74S138A gl 1151
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1972 — R E V IS E D M A R C H 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 54LS 138, S N 54S 138 SN 74LS 138, S N 74S 138A

64LS138

Contextual Info: S N 5 4 LS 13 8 , SN 54S138, S N 74 LS 13 8 , S N 74 S 13 8 A 3-LINE TO 8-LINE D EC OD ERS/DEM U LTIPLEXERS DECEMBER 1972 —REVISED MARCH 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems I I 3 Enable Inputs to Simplify Cascading

connection diagram of ic 74ls138

Abstract: pin diagram of ic 74ls138 pin for 74LS138 74ls138 function sn54ls138 SN54LS13B 74LS138 function table ic 74ls138 74ls138 74S138A
Contextual Info: SN54LS13B, SN54S138, SN74LS138, SN74S13BA 3 LINE TO 8 UNE DECODERSjDEMULTIPLEXERS DECEMBER 1 9 7 2 -R E V IS E D M AR C H 1 9 8 8 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems SN 5 4 LS 1 38 , S N 54S 138 . . . J OR W PACKAG E

Contextual Info: h ig h speed c m o s 1-0F-8 DECODER IDT54/74HCT138 IDT72T338| Integrated Device Technology Inc FEATURES • • • • • • • • • High speed, comparable to bipolar: 11ns typ. CMOS low power levels: 50 typ. Inputs and outputs directly TTL-compatible

Contextual Info: LS TTL DN74LS Series DN74LS138 DN74LS138 M 741^ 3^ 3 -lin e to 8 -lin e Decoders / Demultiplexers • Description P-2 D N 74LS138 is a 3-bit decimal to octal decoder/dem ulti­ plexer w ith enable inputs. ■ Features • • Three types o f enable inputs

74LS138PC

Contextual Info: 138 CONNECTION DIAGRAM PINOUT A & 54S/74S138 54LS/74LS138 bi f rC 1-0F-8 DECODER/DEMULTIPLEXER D E S C R IP TIO N — The '138 is a high speed 1-of-8 decoder/dem ultiplexer. This device is ideally suited for high speed bipolar memory chip select ad­ dress decoding. The m ultiple input enables allow parallel expansion to a

MM74HC138M

Abstract: 74LS138 DATASHEET MM74HC138 and gate 74LS138 74HC 74LS138 M16A M16D MM74HC138MTC MM74HC138N
Contextual Info: Revised February 1999 MM74HC138 3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually

and gate 74LS138

Contextual Info: PRELIMINARY Semiconductor MM54HCT138/MM74HCT138 3-to-8 Line Decoder General Description This decoder utilizes mtcroCMOS Technology, 3.0 micron silicon gate N-weil CMOS, and are well suited to memory address decoding or data routing applications. Both circuits

8205 decoder

Abstract: 74LS138 decoder
Contextual Info: DAC811 For most current data sheet and other product information, visit www.burr-brown.com Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES ● SINGLE INTEGRATED CIRCUIT CHIP ● MICROCOMPUTER INTERFACE: Double-Buffered Latch ● VOLTAGE OUTPUT: ±10V, ±5V, +10V

MM74PC138J

Abstract: MM74PC138N
Contextual Info: microCMOS O'-/ 0 } o o MM74PC138 National Semiconductor MM74PC138 3-Line to 8-Line Decoder/Demultiplexer General Description Features The MM74PC138 is fabricated using National’s microCMOS technology, which offers low power consumption, high noise Immunity, and high speed. The speed of the MM74PC138