74LS10 PIN CONFIGURATION Search Results

74LS10 pin configuration

Contextual Info: GD54/74LS10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 3-input NAND gates. It performs the Boolean functions Y = A B C or Y = Â + B + Ü in positive logic. Vcc 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

74ls163 function table

Contextual Info: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • • • • • • Pin Configuration Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs

pin configuration 74LS10

Abstract: M74HC10P 4000B 74LS10 M74HC10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND G A TE DESCRIPTION The M 74H C 10 is a sem iconductor integrated circu it con­ sisting of three 3-input p o sitive-lo gic PIN CONFIGURATION TOP VIEW NAND, usable as

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Contextual Info: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte­ grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p­

toshiba tc110g

Abstract: 74LS82 74ls150 74LS514 toshiba tc140g 74ls150 pin configuration 74LS273 SC11C1 diode sr45 74LS194 internal circuit diagram
Contextual Info: SIEMENS AKTIEN6ESELLSCHAF 47E » • BS3SbOS 0037405 7 » S I E G General Description Our Sea-of-Gates concept is based on a highperformance CMOS technology, in either 1.5 micron or 1.0 micron transistor gate length. This is equivalent to 1.1 or 0.8 micron effective

XR82C684

Contextual Info: XR82C684
 
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74LS373

Abstract: 8080 cpu module XR82C684
Contextual Info: XR82C684
 
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Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

68C681CJ

Abstract: 68C681 88c681 68c681.h XR-68C681CJ XR68C681
Contextual Info: XR-68C681 CMOS Dual Channel UART DUART August 1997-2 FEATURES • Two Full Duplex, Independent Channels • Interrupt Vector Output on Acknowledge • Asynchronous Receiver and Transmitter • 8 General Purpose Outputs • Quadruple-Buffered Receiver, Dual Buffered

68c681

Abstract: FRTX 88C681 XR68C681
Contextual Info: XR68C681 CMOS Dual Channel UART DUART X^EXqR September 1999-2 FEATURES • Two Full Duplex, Independent Channels • Interrupt Vector Output on Acknowledge • Asynchronous Receiver and Transmitter • 8 General Purpose Outputs • Quadruple-Buffered Receiver, Dual Buffered

ups PURE SINE WAVE schematic diagram

Abstract: ad9850 am modulation quality FM TRANSMITTER AD9854 DDS based CLOCK GENERATOR 10MHZ ad9850 fm modulation 74HC74 optical quadrature encoder ad9850 AD985X LMX1501A 3 phase ups PURE SINE WAVE schematic diagram
Contextual Info: A Technical Tutorial on Digital Signal Synthesis a Copyright  1999 Analog Devices, Inc. 1 Outline Section 1. Fundamentals of DDS technology Page 5 Overview DDS Advantages Theory of operation Circuit architecture Tuning equation Elements of DDS circuit functionality and capabilities

Truth Table 7485 2 bit comparator

Abstract: IC 7400 pin diagram Truth Table 7485 ic D flip flop 7474 pin DIAGRAM OF IC 7474 74152 data sheet Multiplexer 74152 pin diagram of ic 74ls00 pin diagram for IC 7485 IC TTL 7400 propagation delay
Contextual Info: TM ACTIVE-CAD Real-Time Interactive CAE Tools Logic Simulator User’s Guide Seventh Edition Revision 2 Automated Logic Design Company, Inc. 3525 Old Conejo Rd. #111 Newbury Park, CA 91320 Phone 805 499-6867 Fax (805) 498-7945 Seventh Edition Revision 2, January 15, 1996

memory interfacing to mp 8085 8086 8088

Abstract: 82c684cj 82c684 block diagram of processor 80486 intel 8085 and motorola 6800 1C16 LS 74LS138 function and details in microprocessor 8085
Contextual Info: XR -82C 684 C Y V I B t / V i r \ I C M O S Q uad C hannel U AR T Q U A R T August 1997-2 FEATURES • Four Full-Duplex, Independent Channels • Two Multi-function 16-bit Counter/Timers • Asynchronous Receiver and Transmitter • • Quadruple-Buffered Receivers and Transmitters