74HS Search Results

Contextual Info: 74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

Contextual Info: 74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

15-V

Abstract: A115-A C101 SN74HSTL16919
Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

Contextual Info: 74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

74HS164

Abstract: ULF2481 "LED Bar Graph" LED bar graph ULF-2481NX ULF-2481 HDR2X1 HDR5X2 thermistance 2481N
Contextual Info: A B 0805 ANODE2 4 ANODE5 6 ANODE3 8 ANODE4 R2 R43 Q1 PNP Y2 10K 1 2 Q2 PNP Y2 NC1 NC2 NC3 9 10 12 R44 2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 4 10K R4 P4[2] P4[2] 1 0805 14 16 13 3 5 11 15 7 R3 P4[1] P4[1] CATHODE_A CATHODE_B CATHODE_C CATHODE_D CATHODE_E

Contextual Info: 74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

Contextual Info: 74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

74HS5

Contextual Info: 50 CO NNECTIO N DIAGRAMS PINOUT A Ò f f r 1 g- 54/7450 ''54H/74H50 o H ^ / z EXPANDABLE DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE PINOUT B ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, T a = 0°C to +70° C V cc = +5.0 V ±10%,

d1684

Abstract: D 799 IQM584450 529t
Contextual Info: =;E/3 -AC mri^. EB?>9 EF6F: D:?6J ;OLZ[XOY Fbe^ Lh2>E5778<5 | Eq\^ee^gm ma^kfZe ]^lb`gbg`0 ehZ] \nkk^gm 7A0 KZq2 \nkk^gm ni mh 9A pbma 94+ ]nmr Zg] 5Hs mh 74 Hs Fbe^ Lh2>P944<;:=8 | Hb`a lnk`^ k^lblmZg\^ | Db^e^\mkb\ lmk^g`ma 8444T | EKC i^k_hkfZg\^ f^^ml CE k^jnbk^f^gm

15-V

Abstract: 74HSTL16918DGGRG4 SN74HSTL16918 SN74HSTL16918DGGR
Contextual Info: 74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

Contextual Info: 74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

220v AC voltage stabilizer schematic diagram

Abstract: LG color tv Circuit Diagram tda 9370 1000w inverter PURE SINE WAVE schematic diagram schematic diagram atx Power supply 500w TV SHARP IC TDA 9381 PS circuit diagram wireless spy camera 9744 mini mainboard v1.2 sony 279-87 transistor E 13005-2 superpro lx
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 AD9272 Analog Front End, iMEMS Accelerometers & Gyroscopes . . . . . . 782, 2583 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-528 Acceleration and Pressure Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2585

Contextual Info: 74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

15-V

Abstract: 74HSTL16918DGGRG4 SN74HSTL16918 SN74HSTL16918DGGR
Contextual Info: 74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

smd code dtc 143 es

Abstract: 79h15 DECT siemens xtal abt KM29N32000
Contextual Info: SIEMENS ICs for Communications Digital Answering Machine with Speakerphone SAM SP PSB 4850 Version 2.1 Target Specification 03.97 T4850-XV21 -S1 -7600 PSB 4850 Revision History: Current Version: Version 2.1 Previous Version: Target Specification 07.96 V1.1

Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

SN74HSTL16919

Abstract: 15-V A115-A C101
Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

15-V

Abstract: SN74HSTL162822
Contextual Info: 74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

Contextual Info: 74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications

15-V

Abstract: SN74HSTL162822
Contextual Info: 74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series