74HC112 Search Results
74HC112 Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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CD74HC112NSR |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SO -55 to 125 |
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SN74HC112DR |
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Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85 |
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CD74HC112E |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
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CD74HC112M96 |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
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CD74HC112MT |
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High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
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74HC112 Datasheets (24)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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74HC112 |
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Negative-edge trigger | Original | 90.34KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112D |
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dual JK flip-flop with set and reset negative-edge trigger | Original | 109.44KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112D | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112D,652 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112D,653 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112DB |
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dual JK flip-flop with set and reset negative-edge trigger | Original | 109.44KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112DB | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112DB,112 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Tube | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112DB,118 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112DB-T |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112DB-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112D-T |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112D-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112N |
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dual JK flip-flop with set and reset negative-edge trigger | Original | 109.44KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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74HC112N | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112N,652 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112PW |
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dual JK flip-flop with set and reset negative-edge trigger | Original | 109.44KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112PW | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112PW,112 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Tube | Original | 90.33KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC112PW,118 |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Reel Pack, SMD, 13" | Original | 90.33KB | 15 |
74HC112 Price and Stock
onsemi MC74HC112ADTR2GIC FF JK TYPE DBL 1-BIT 16-TSSOP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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MC74HC112ADTR2G | Cut Tape | 3,989 | 1 |
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MC74HC112ADTR2G | Reel | 14 Weeks | 7,500 |
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MC74HC112ADTR2G | 876 |
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MC74HC112ADTR2G | Reel | 2,500 |
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MC74HC112ADTR2G | 194,589 | 1 |
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MC74HC112ADTR2G | 15 Weeks | 2,500 |
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MC74HC112ADTR2G | 16 Weeks | 2,500 |
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MC74HC112ADTR2G | 7,500 |
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Nexperia 74HC112D,653IC FF JK TYPE DOUBLE 1BIT 16-SO |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC112D,653 | Digi-Reel | 2,828 | 1 |
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74HC112D,653 | Reel | 8 Weeks | 5,000 |
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74HC112D,653 | 2,779 |
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74HC112D,653 | 669 | 1 |
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74HC112D,653 | Reel | 2,500 |
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74HC112D,653 | 2,330 | 1 |
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74HC112D,653 | 10 Weeks | 2,500 |
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74HC112D,653 | 2,500 | 10 Weeks | 2,500 |
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74HC112D,653 | 5,000 | 1 |
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onsemi MC74HC112ADTGIC FF JK TYPE DBL 1-BIT 16-TSSOP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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MC74HC112ADTG | Tube | 1,911 | 1 |
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MC74HC112ADTG | Tube | 14 Weeks | 6,048 |
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MC74HC112ADTG | 851 |
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MC74HC112ADTG | Bulk | 1,152 |
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MC74HC112ADTG | 63,744 | 1 |
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MC74HC112ADTG | 1 | 1 |
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Texas Instruments SN74HC112NIC FF JK TYPE DBL 1-BIT 16-PDIP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74HC112N | Tube | 1,355 | 1 |
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SN74HC112N | 3,270 |
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SN74HC112N | Bulk | 36 | 1 |
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SN74HC112N | 608 |
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SN74HC112N | 6,709 | 1 |
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SN74HC112N | 141 | 1 |
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SN74HC112N | 992 |
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SN74HC112N | 2,040 |
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Texas Instruments SN74HC112DTIC FF JK TYPE DBL 1-BIT 16-SOIC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74HC112DT | Digi-Reel | 789 | 1 |
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SN74HC112DT | 1,057 |
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74HC112 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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IC 74HC112
Abstract: 74HC112
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CD54/74HC112, CD54/74HCT112 SCHS141A HC112 HCT112 loSZZU001B, SDYU001N, SCET004, SCAU001A, CD74HC112E IC 74HC112 74HC112 | |
74ls112 pin diagram
Abstract: 74HC112
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OCR Scan |
GD54/74HC112, GD54/74HCT112 54/74LS112. 74ls112 pin diagram 74HC112 | |
74HC112 pin diagram
Abstract: 74HC112 74HC112D IC 74HC112
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OCR Scan |
MC54/74HC112 74HC112 pin diagram 74HC112 74HC112D IC 74HC112 | |
MC54HC112Contextual Info: MOTOROLA • SEMICONDUCTOR TECHNICAL DATA MC54/74HC112 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS The M C 54/74H C 11 2 is id entical in p in o u t to the LS112. The device in p u ts are c o m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, th e y are c o m p a tib le |
OCR Scan |
MC54/74HC112 MC54HC112 MC74HC112 LS112. HC112 | |
74ls112 pin diagramContextual Info: TOSHIBA LOG IC/MEMOR Y IME 0 I ^0 1 724 0 0 0 1 0 0 3 0 o| — 74HC112P/F TC 74HC112P/F DUAL J-K FLIP FLOP WITH PRESET AND CLEAR The 74HC112 is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2M0S technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining |
OCR Scan |
TC74HC112P/F 74HC112P/F TC74HC112 TC74H C112P/F 74ls112 pin diagram | |
74HC112
Abstract: data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR
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HC112 HCT11 CD54/74HC112, CD54/74HCT112 SCHS141B HC112 HCT112 74HC112 data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR | |
74HC112Contextual Info: • MOTOROLA SEMICONDUCTOR M TECHNICAL DATA IH0T4 blE D b3b75se OCHITHO 3b4 otorola se clogic MC54/74HC112 Dual J -K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620*09 High-Performance Silicon-Gate CMOS T he M C 54/74H C 11 2 is id en tic a l in p in o u t to th e L S 112. T he device in p u ts are |
OCR Scan |
b3b75se MC54/74HC112 54/74H HC112 b3b72S2 74HC112 | |
74HC112
Abstract: IC 74HC112
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CD54/74HC112, CD54/74HCT112 SCHS141C HC112 HCT11 74HC112 IC 74HC112 | |
CD54HC112F3A
Abstract: CD54HCT112F3A CD74HC112E CD74HCT112E IC 74HC112 74HC112
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HC112 HCT11 CD54/74HC112, CD54/74HCT112 SCHS141A HC112 HCT112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HCT112E IC 74HC112 74HC112 | |
8408801EAContextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141E Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised January 2003 |
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CD54/74HC112, CD54/74HCT112 SCHS141E HC112 HCT112 59628970201EA CD54HCT112F3A 5962View 8970201EA 8408801EA | |
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141E Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised January 2003 |
Original |
CD54/74HC112, CD54/74HCT112 SCHS141E HC112 HCT112 | |
IC 74HC112
Abstract: HC112
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Original |
CD54/74HC112, CD54/74HCT112 SCHS141B HC112 HCT112 SDYZ001A, CD74HC112E CD74HC112M96 CD74HC112NSR CD74HC112PWR IC 74HC112 | |
IC 74HC112
Abstract: 74HC112 pin diagram motorola 5118 setup 74HC112A 74HC112
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OCR Scan |
MC54/74HC112 LS112. HC112 MC54/74HC112 IC 74HC112 74HC112 pin diagram motorola 5118 setup 74HC112A 74HC112 | |
54HC112Contextual Info: SN54HC112, 74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 02684, DECEMBER 1982-REVISED SEPTEMBER 1987 SN54HC112 . . . J PACKAGE 74HC112 . . . D OR N PACKAGE TOP VIEW ] 1CLK C 1 O l 6 H V CC i k C 2 15 3 1CLR 14 H 2CLR u [ 3 |
OCR Scan |
SN54HC112, SN74HC112 1982-REVISED 300-mil SN54HC112 SN74HC112 SN54HC112 54HC112 | |
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5555 FAIRCHILD optocoupler
Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
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SCYB017A A010203 5555 FAIRCHILD optocoupler MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N | |
siemens b 58 468 la intel 80
Abstract: PEB 2261 ic 8279 rabbit 5000 ELIC - PEF 20550 PCR 406 J RDD 17-33 TSN2 SICOFI PEB 2261 N V2.0 PEF 2261 N
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T2055-0V13-M1-7600 siemens b 58 468 la intel 80 PEB 2261 ic 8279 rabbit 5000 ELIC - PEF 20550 PCR 406 J RDD 17-33 TSN2 SICOFI PEB 2261 N V2.0 PEF 2261 N | |
74HC9046
Abstract: 74HCT4050 74hct7014 74HCT4049 74HC7541 74hct133 74HC9046A 74HC90 74HCT4059 74HC5555
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74HCU04 74HCTU04 74HC00 74HCT00 74HC02 74HCT02 74HC03 74HCT03 74HC04 74HC86 74HC9046 74HCT4050 74hct7014 74HCT4049 74HC7541 74hct133 74HC9046A 74HC90 74HCT4059 74HC5555 | |
HC112MContextual Info: I R C H I L D S E M I C O N D U C T O R TM 74VHC112 Dual J-K Flip-Flops with Preset and Clear General Description The VHC112 is an advanced high speed C M OS device fa b ricated w ith silicon gate C M OS technology. It achieves the high-speed operation sim ilar to equivalent Bipolar Schottky |
OCR Scan |
74VHC112 VHC112 HC112M | |
74hc112Contextual Info: M54HC112 74HC112 SCSTHOMSON m DUAL J-K FLIP FLOP WITH PRESET AND CLEAR a HIGH SPEED fMAX = 59 MHz Typ. at VCC= 5V LOW POWER DISSIPATION lCC = 2 (iA at Ta = 25°C • HIGH NOISE IMMUNITY VNIH = VNIL= 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS |
OCR Scan |
M54HC112 M74HC112 54/74LS112 M54/74HC112 M54HC112/M74HCis M54/74HC112 74hc112 | |
Contextual Info: SbE D • 7 * ^ 2 3 7 OGB'îflm 2S7 ■ S G T H S G S -T H O M S O N M 5 4 H C Ï 12 LiOT KDD i M 7 4 H C 1 12 6 S-THOMSON ’T-HÙ-ÔT-OT DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED fMAX = 59 MHz (Typ. at VCC= 5V LOW POWER DISSIPATION Ice = 2 jiA at TA = 25°C |
OCR Scan |
280/o 54/74LS112 74HC112 S-10216 | |
k2645
Abstract: k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417
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MK135 MK136 MK137 MK138 MK139 MK140 Mk142 MK145 MK155 157kr k2645 k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417 | |
TDA0161 equivalent
Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
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OCR Scan |
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"J-K Flip flops"
Abstract: 74HC112 74VHC112 74VHC112M 74VHC112MTC 74VHC112SJ M16A M16D MTC16 VHC112
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74VHC112 200MHz VHC112 74HC112 74VHC112 "J-K Flip flops" 74HC112 74VHC112M 74VHC112MTC 74VHC112SJ M16A M16D MTC16 | |
EZ 639
Abstract: IC74HC02 memory programer IC74HC148 74HC4072 78F9234 CT-780CT-207 IC74HC11 ez 643 IC74HC138
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CT-780 U17656CA4V0UM CT-781 CT-780CT-207 EZ 639 IC74HC02 memory programer IC74HC148 74HC4072 78F9234 CT-780CT-207 IC74HC11 ez 643 IC74HC138 |