74HC* OPEN DRAIN BUFFER Search Results

Contextual Info: 74HC/HCT9114 MSI SUPERSEDES DATA OF MARCH 1988 NINE WIDE SCHMITT TRIGGER BUFFER; OPEN DR AIN OUTPUTS; INVERTING FEATURES • • • TYPICAL Schmitt trigger action on all data inputs Output capability: standard open drain lc c category: MSI GENERAL DESCRIPTION

Contextual Info: 74HC/HCT9115 MSI V NINE WIDE SCHMITT TRIGGER BUFFER; OPEN DR AIN OUTPUTS FEATUR ES • • • S ch m itt trigger action on all data inputs O u tp u t ca p a b ility: standard open drain lc c category: MSI TYPICAL SYMBOL <p h U tp l z propagation delay An to Y n

Contextual Info: 74HC/HCT9114 MSI SUPERSEDES D A T A OF M ARCH 1988 N IN E W IDE S C H M IT T T R IG G E R B U F F E R ; OPEN D R A IN OUTPUTS; IN V E R T IN G FEA TU R ES • • • * Schm itt trigger action on all data inputs Output capability: standard open drain lc c category: MSI

IC 74hc266

Abstract: 74hc266 74LS7266 HC266 hc7266 M74HCXXXB1R M74HCXXXC1R 74hc26 exclusive nor
Contextual Info: r z 7 S C S -T H O M S O N ^7# M54/,74HC266 R»«@gLiOT 5 [«l_ M 54/74HC 7266 HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN HC7266 QUAD EXCLUSIVE NOR GATE • HIGHSPEED tpD = 10 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 HA (MAX.) AT T a = 25 °C

74HC09

Abstract: K2108
Contextual Info: r z T S G S -T H O M S O N M 5 4 H £ 2 2 [M r a [E L H @ [* S M 74HC 09 QUAD 2-INPUT AND GATE OPEN DRAIN HIGHSPEED 6 ns (TYP.) A T V cc = 5 V LOW POWER DISSIPATION Ice = 1 (iA (MAX.) AT Ta = 25 "C HIGH NOISE IMMUNITY V n ih = V n il = 28 % Vcc (MIN.)

Contextual Info: INTEGRATED CIRCUITS DAT For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT9115

74HC/HCT/HCU/HCMOS Logic Family Specifications

Abstract: 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC 74HCT
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT9115

on 5295 transistor

Abstract: on 5295 MM74HC03N MM74HC 54HC 54LS 74HC 74LS C1995 MM54HC03
Contextual Info: MM54HC03 MM74HC03 Quad 2-Input Open Drain NAND Gate General Description Features These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits All gates have buffered outputs All devices have high noise immunity and the ability to drive 10

Contextual Info: INTEGRATED CIRCUITS DAT For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT9114

74HC/HCT/HCU/HCMOS Logic Family Specifications

Abstract: TTL Schmitt-Trigger LOW POWER SCHOTTKY IC06 74HC/HCT/HCU/HCMOS Logic Package Information 74HC/HCT/HCU/HCMOS Logic Package Information 74HC/HCT/HCU/HCMOS Logic Package Outlines 74hc* open drain buffer 74HC books schmitt trigger cmos IC06 74HC/HCT/HCU/HCMOS Logic Package Outline 74HCT
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT9114

74HC07

Contextual Info: r z 7 SCS-THOMSON ^7# M54HC07 M74HC07 HEX BUFFER OPEN DRAIN • HIGHSPEED tpD = 5 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 |iA (MAX.) AT Ta = 25 "C ■ HIGH NOISE IMMUNITY V nih = Vnil = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS

aaBO

Abstract: on 5295 74HC MM54HC MM54HC03 MM74HC MM74HC03
Contextual Info: MM54HC03/MM74HC03 Quad 2-Input Open Drain NAND Gate General Description Features These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All de­

u 74 hct 74

Contextual Info: 74H C /H C T 91 1 5 MSI SUPERSEDES DATA OF MARCH 1988 NINE WIDE SCHMITT TRIGGER BUFFER; OPEN DRAIN OUTPUTS FEA TU R ES • • • T Y P IC A L Schm itt trigger action on all data inputs O utput capability: standard open drain ICC category: MSI SYM BO L

74HC07

Abstract: 74HC07B 74ls07 buffer 74HC07B1R M74HC07M
Contextual Info: f Z 7 SCS-THOMSON Ä 7 # [*« L iO T iO O S M54HC07 M74HC07 HEX BUFFER OPEN DRAIN • HIGH SPEED tPD = 5 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 1 |xA (MAX.) AT Ta = 25 "C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

74HC07

Abstract: M54HC07 M54HC07F1R M74HC07 M74HC07B1R M74HC07C1R M74HC07M1R
Contextual Info: M54HC07 M74HC07 HEX BUFFER OPEN DRAIN . . . . . . HIGH SPEED tPD = 5 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS WIDE OPERATING VOLTAGE RANGE

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

il6ac

Abstract: led 7 doan HC40S1A bc55a Analog multiplexer 4051 YJ 162A S691 oscillator DUAL led 7 doan HC69SA cb 4040
Contextual Info: 2. H IG H GATE SPEED CMOS N AN O NOR AND OR INVERTER, BUFFER EXCLUCIVE O R / NOR SCHIMITT TRIGGER MULTI FUNCTION LEVELSHIFTER FLIP-FLOP SELECTION G U ID E HCOOA HCTOOA HC03A HC10A HC20A HC30A HC132A HC133A HC02A HCT02A HC27A HC4002A HC4078A HC08A HCT08A HC09A HC11A HC21A

Contextual Info: Technical Data CD54/74HC03 CD54/74HCT03 File Number 1832 High-Speed CMOS Logic Quad 2-Input NAND Gate With Open Drain Type Features: * Buffered inputs • Typical propagation delay = 8 ns @ Vcc = 5 V, C l = 15 pF, 7» = 25° C ■ O utput pull-up to 10 V FUNCTIONAL DIAGRAM

74HC07

Abstract: CI 74ls07 C07F C07M1
Contextual Info: ms4HC07 M74HC07 SGS-THOMSON Rffl0 » [iy iM ! 0 gi HEX BUFFER (OPEN DRAIN) • HIG HSPEED 1p d = 5 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 1 M-A (MAX.) AT Ta = 25 °C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % V cc (MIN.) ■ OUTPUT DRIVE CAPABILITY

Contextual Info: National January 1988 Semiconductor MM54HC03/MM74HC03 Quad 2-Input Open Drain NAND Gate General Description Features These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS

ci mm74hc

Contextual Info: January 1988 Semiconductor MM54HC03/MM74HC03 Quad 2-Input Open Drain NAND Gate General Description Features These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS

hex buffer

Abstract: MM74HC05M
Contextual Info: NPA Number 021 January 2013 New Product Announcement Announcement LOGIC Advanced and High Speed CMOS Logic Families added to Logic Portfolio Description Four families of parts including: 74HC -High speed CMOS • 2.0 V to 6.0 V • 4 mA drive capability  9 ns typical propagation time.

Contextual Info: M54HC03 M74HC03 T S G S -T H O M S O N QUAD 2-INPUT OPEN DRAIN NAND GATE • LOW POWER DISSIPATION lCC = 1 /*A MAX. at Ta = 25°C .-" \ ■ HIGH NOISE IMMUNITY V nih = V nil = 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ SYMMETRICAL OUTPUT IMPEDANCE

74LS03

Abstract: M54HC03 M54HC03F1R M74HC03 M74HC03B1R M74HC03C1R M74HC03M1R 74HC03
Contextual Info: M54HC03 M74HC03 QUAD 2-INPUT OPEN DRAIN NAND GATE . . . . . . . HIGH SPEED tPZ = 5 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS