74F273SC Search Results

TTL 1-of-8 encoder

Abstract: 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC
Contextual Info: 1/2 TTL LOGIC 74F SERIES 74F SERIES • 74F: EXCELLENT SPEED/POWER CONSUMPTION COMBINATION Part Number Description SQP £ ea. Gates & Inverters 74F00SC Quad 2-Input NAND Gate 74F02SC Quad 2-Input NOR Gate 74F04SC Hex Inverter 74F08SC Quad 2-Input AND Gate

Contextual Info: 273 National Semiconductor 54F/74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (fflR) inputs load and reset

74F273

Abstract: 74F273PC 74F273SC 74F273SJ 74F373 74F374 74F377 M20D
Contextual Info: Revised September 2000 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

54F273DM

Abstract: 74F273 74F273PC 74F273SC 74F273SJ F373 F374
Contextual Info: 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously

74F273

Contextual Info: 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously

ti 261

Abstract: 74F273
Contextual Info: 54F273,74F273 54F273 Octal D Flip-Flop Literature Number: SNOS182A 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset

Contextual Info: S E M IC O N D U C T O R -n 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all

BR 13005

Abstract: CERAMIC LEADLESS CHIP CARRIER 54F273DM 74F273PC 74F273SC F373 F374 J20A
Contextual Info: Semiconductor M ay 1995 5 4 F /7 4 F 2 7 3 O ctal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D -type -flip-flops w ith in­ dividual D inputs and Q outputs. The com m on buffered C lock CP and M aster R eset (MR) inputs load and reset

CERAMIC LEADLESS CHIP CARRIER

Abstract: 54F273DM 74F273 74F273PC 74F273SC F373 F374 J20A
Contextual Info: S E M IC O N D U C T O R tm 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all

lm 7223

Contextual Info: co is. CM National Semiconductor 54F/74F273 Octal D Flip-Flop General Description Features The 'F273 has eight edge-triggered D-type flip-flops with in­ dividual 0 inputs and O outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset

74F273SC

Abstract: 74F273 74F273PC 74F273SJ 74F373 74F374 74F377 M20D
Contextual Info: Revised August 1999 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

74F273

Abstract: 54F273DM 54F273FM 74F273PC 74F273SC 74F273SJ F373 F374
Contextual Info: 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

Contextual Info: A I R C H I L D p PriM9H8!! i QQQ Revised A ugust 1999 EMICONDUCTGRTM 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D -type flip-flops with individual D inputs and Q o utp uts. The com m on buffered C lock CP and M aster Reset (MR) inputs load and reset

Contextual Info: Semiconductor May 1995 5 4 F /7 4 F 2 7 3 O ctal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset