74F114SC Search Results

74F114SC Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
74F114SC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears	Original	PDF	55.88KB	6
74F114SC		National Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears	Original	PDF	122.26KB	6
74F114SC		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.	Historical	PDF	35.59KB	1
74F114SCX		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop w/Common Clocks and Clears	Original	PDF	55.87KB	6

74F114SC Price and Stock

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onsemi 74F114SCX 74F114SCX
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical ()	74F114SCX		2,849		2,104	1 - 10 - 100 - 1000 - 10000 $0.16	Buy Now
	74F114SCX		2,500		2,104	1 - 10 - 100 - 1000 - 10000 $0.16	Buy Now
Fairchild Semiconductor Corporation 74F114SC J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	74F114SC		3,698		1	1 - 10 - 100 $0.08 1000 $0.07 10000 $0.06	Buy Now
Fairchild Semiconductor Corporation 74F114SCX J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	74F114SCX		5,349		1	1 - 10 - 100 $0.17 1000 $0.14 10000 $0.13	Buy Now

74F114SC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
TTL 1-of-8 encoder Abstract: 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC Contextual Info: 1/2 TTL LOGIC 74F SERIES 74F SERIES • 74F: EXCELLENT SPEED/POWER CONSUMPTION COMBINATION Part Number Description SQP £ ea. Gates & Inverters 74F00SC Quad 2-Input NAND Gate 74F02SC Quad 2-Input NOR Gate 74F04SC Hex Inverter 74F08SC Quad 2-Input AND Gate	Original	74F164ASC 74F194SC 74F299SC 74F350SC 74F378SC 74F379SC 74F398SC 74F399SC 74F675ASC 74F676SC TTL 1-of-8 encoder 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC	PDF
jk flip flop Abstract: 74F114 74F114PC 74F114SC C1995 F114 M14A N14A Contextual Info: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs Synchronous state changes are initiated by the falling edge of the clock Triggering occurs at a voltage level of the clock and is not directly related	Original	74F114 jk flip flop 74F114 74F114PC 74F114SC C1995 F114 M14A N14A	PDF
Contextual Info: National Semiconductor 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with com mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering oc	OCR Scan	74F114	PDF
Contextual Info: p P r iM 9 H 8 ! ! iQ Q Q Revised A ugust 1999 EMICONDUCTGRTM 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description S im ultaneous LO W signals on S q and C q force both Q and The 74F114 contains tw o high-speed JK flip-flops with	OCR Scan	74F114	PDF
Contextual Info: August 1995 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with com mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering oc	OCR Scan	74F114	PDF
74F114 Abstract: 74F114PC 74F114SC M14A MS-001 N14A Contextual Info: Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not	Original	74F114 74F114 74F114PC 74F114SC M14A MS-001 N14A	PDF
74F114 Abstract: 74F114PC 74F114SC F114 M14A N14A Contextual Info: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at	Original	74F114 74F114 74F114PC 74F114SC F114 M14A N14A	PDF
Contextual Info: National Semiconductor 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 'F114 contains two high-speed JK flip-flops with com mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering oc	OCR Scan	74F114	PDF