74AUP2G80DC Search Results

Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 8 — 21 January 2013 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

Dual D-type flip-flop positive-edge trigger

Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 03 — 28 March 2008 Product data sheet 1. General description The 74AUP2G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

74AUP2G80

Abstract: 74AUP2G80DC 74AUP2G80GD 74AUP2G80GT JESD22-A114E JESD78
Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 04 — 2 June 2008 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 6 — 7 December 2011 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

74AUP2G80

Abstract: 74AUP2G80DC 74AUP2G80GT JESD78
Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 5 — 5 October 2010 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

VSSOP8

Abstract: XSON8 74AUP2G80 74AUP2G80DC 74AUP2G80GM 74AUP2G80GT MO-187
Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 01 — 25 August 2006 Product data sheet 1. General description The 74AUP2G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP2G80DC

Abstract: SN74AUC2G80DCTR 74AUP2G80 74AUP2G80GM 74AUP2G80GT SN74AUC2G80
Contextual Info: SLG74LB2G80 GreenLIBTM DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP General Description Features The GreenLIB provides a low-power, low-voltage dual • Pb-Free / RoHS Compliant positive-edge-triggered D-type flip-flop. When data at the • Halogen-Free data D input meets the setup time requirement, the data is

74AUP2G80

Abstract: 74AUP2G80DC 74AUP2G80GM 74AUP2G80GT JESD22-A114E MO-187
Contextual Info: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 02 — 1 August 2007 Product data sheet 1. General description The 74AUP2G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock