74AUP2G00DC Search Results

74AUP2G00DC

Abstract: 74AUP2G00 74AUP2G00GM 74AUP2G00GT MO-187
Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 01 — 25 August 2006 Product data sheet 1. General description The 74AUP2G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74aup2g00dc

Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 02 — 15 May 2007 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74aup2g00dc

Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 6 — 1 December 2011 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP2G00DC

Abstract: 74AUP2G00 74AUP2G00GT JESD78
Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 5 — 21 October 2010 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74aup2g00dc

Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 03 — 3 April 2008 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP2G00DC

Abstract: 74AUP2G00 74AUP2G00GD 74AUP2G00GT JESD22-A114E JESD78
Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 04 — 5 June 2008 Product data sheet 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74aup2g00dc

Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 7 — 8 June 2012 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP2G00

Abstract: 74LVC2G00 NC7WP00 NC7WZ00 NL27WZ00 SN74AUC2G00 SN74AUP2G00 SN74LVC2G00 74aup2g00dc
Contextual Info: SLG74LB2G00 GreenLIBTM DUAL 2-INPUT NAND GATE General Description The GreenLIB provides the dual 2-input NAND function. Features • Pb-Free / RoHS Compliant • Halogen-Free This device ensures a very low static and dynamic • TDFN-8 Package power • Low static power consumption IDD = 1A

Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 7 — 8 June 2012 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74aup2g00dc

Contextual Info: 74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall