74AUP1G240GW Search Results

Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 4 — 29 June 2012 Product data sheet 1. General description The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH level at pin OE

74AUP1G240GW

Abstract: MO-203 74AUP1G240 74AUP1G240GF 74AUP1G240GM
Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 4 — 29 June 2012 Product data sheet 1. General description The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH level at pin OE

74AUP1G240

Abstract: 74AUP1G240GF 74AUP1G240GM 74AUP1G240GW
Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 2 — 13 September 2010 Product data sheet 1. General description The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH level at pin OE

Contextual Info: 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 3 — 24 November 2011 Product data sheet 1. General description The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH level at pin OE