74AS13 Search Results

74AS131

Abstract: H 349
Contextual Info: DM54AS131/74AS131 National JutSemiconductor 74AS131 3-to-8 Line Decoders/Demultiplexers with Address Registers General Description Features The DM54/74AS131 is a 3-to-8 line decoder/dem ultiplexer with registers on the three address inputs. When the clock

16-LIN

Contextual Info: a >i MITSUBISHI ASTTLs M 74AS13SP 3-LINE TO 8-LINE DECODER/DEMULTIPLEX ER DESCRIPTION T h e M 7 4 A S 1 3 8 P is a s e m ic o n d u c to r in te g ra te d c irc u it of a 3 - lin e - to - 8 - lin e d e c o d e r /d e m u ltip le x e r w ith PIN CONFIGURATION TOP VIEW

74AS13

Abstract: ls 138 74AS138 LS138 SN54ALS138
Contextual Info: SN74ALS138, SN 74AS13«, SN54ALS138, SN54AS138 3-LINE TO B-LINE DECODERS/DEMULTIPLEXERS 02661, APRIL 1982 - REVISED MAY 1986 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 5 4A LS 138, S N 6 4A S 1 38 . . J PACKAGE S N 74A LS 138, S N 7 4A S 1 38

74AS138

Contextual Info: PRELIMINARY DM54AS138/74AS138 3-to-8 Line Decoder/ Demultiplexer General Description Features The DM54/74AS138 c ircuit is designed to be used in high perform ance memory decoding or data routing applica­ tions requiring very short propagation delay times. In high

Contextual Info: TEXAS INSTR 0=^1723 oaaBü? 1 5SE D LOGIC SN54ALS131, SNB4AS131A, SN74ALS131, 74AS131A 3-LINE TO 8-LINE DECODERSIDEMULTIPLEXERS WITH ADDRESS REGISTERS r-<U.-2('55 D 2 6 6 1 , A PRIL 1 9 8 2 - R E V IS E D M AY 1986 SN54ALS131, SN54AS131A . . . J PACKAGE

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320P14

Abstract: TMS320LC15 cy7c291 TMS320C1x TMS320C10 TMS320C10-14 TMS320C10-25 TMS320C14 TMS320C15 TMS320E14
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

74LS90

Abstract: AM6012 LT1022 LTC1099 LTC1099A LTC1099ACN LTC1099AIN LTC1099CN 20pin 4bit adc
Contextual Info: LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter A/D . An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the

application of 74LS90

Abstract: 74as00
Contextual Info: LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter A/D . An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the

74LS244 diagram

Abstract: 74LS31 74LS373 Decoder pin BYU29 TMS32010 74ALS02 74ALS32 ADC80Z 74F245 74LS373
Contextual Info: Chapter 5 Theory of Operation The AIB has three basic input/output I/O ports: an analog I/O port, an expansion I/O port, and an extended memory interface port. The analog input port consists of an anti-aliasing filter, a sample and hold circuit, and an analog-to-digital (A/D) converter. The analog output port consists of a digital-toanalog converter, a smoothing filter, an an optional audio output amplifier. The expansion input port provides sixteen buffered inputs, and the expansion output port

TMS320LC15

Abstract: TMS320P14 TMS320C16
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

DSP stereo based on tms320

Abstract: SPRU031D DSP101 class d Sinus inverter circuit diagram schematics TMS320C30 TMS320C30-40 TMS320C31 TMS320C31-40 TMS320C31-50 TMS320C31PQA
Contextual Info: TMS320C3x User’s Guide 2558539-9721 revision J October 1994 TMS320C3x User’s Guide 1994 Digital Signal Processing Products Printed in U.S.A., October 1994 2558539-9761 revision J SPRU031D User’s Guide TMS320C3x 1994 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

TMS320LC15

Abstract: TMS320C16 TMS320P14
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320LC15

Abstract: LC-15 C16S TMS320P14
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

Architecture of TMS320C28

Abstract: fetal monitor device circuit diagrams texas instrument 74HC14 TMS320 TMS32010 TMS320C10 TMS320C25 TMS320C25-50 TMS320C26 TMS320C28
Contextual Info: TMS320C2x User's Guide 1604907-9761 revision C January 1993 Running Title—Attribute Reference Chapter 1 Introduction The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array

TMS320P14

Abstract: TMS320LC15 TMS320C16
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

74ALS131

Contextual Info: SIM54ALS131, SN54AS131A, SN74ALS131, 74AS131A 3 LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS REGISTERS D 2 6 6 1 . APRIL 1 9 8 2 -R E V IS E D M A Y 1 9 8 6 • SN 54A LS131, SN 54A S 131A . . . J PACKAGE SN 74ALS131, S N 74A S 131A . . . D OR N PACKAGE

Contextual Info: LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ U ■ The LTC 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter A/D . An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the

Contextual Info: SN54ALS131, SN54AS131A, SN74ALS131, 74AS131A 3 LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS REGISTERS D 2 6 6 1 , APRIL 1 9 8 2 -R E V IS E D M A Y 1986 • I • Combines Decoder and 3-Bit Address Register I I • Incorporates 2 Enable Inputs to Simplify

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320P14

Abstract: mcl plc -3-1 TMS320LC15 876-3308 td64 TMS320C16
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM

TMS320LC15

Abstract: TMS320P14 TMS320C16
Contextual Info: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM