74LS74 Search Results

74LS147

Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
Contextual Info: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are

F7474PC

Abstract: 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D 7474PC IC 74LS74 pin IC 7474 74LS74PC IC 7474 flipflop
Contextual Info: 74 C O N N E C T IO N DIAGRAM S P IN O U T A 54/7474 < ? / / 6 ' \/54H/74H74 t f e. j w w^4S/74S74 £>/, o 'b, U34LS/74LS74 ^ ^ < - 3 ^ — "Si / / DUAL D-TYPE POSITIVE ED G e"TRIGGERED FLIP-FLOP P IN O U T B DESCRIPTIO N — The ’74 devices are dual D-type flip-flops with Direct C le a r

Contextual Info: H D 74LS74A . Dual D-type Positive Edge-triggered Flip-Flops with Preset and Clear • P IN ARRANGEMENT ■FU N C T IO N TABLE O utputs Inputs P re s e t C lear Clock D Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H X Qo Qo L Notes) H; high level, L; low level, X; irrelevant

Contextual Info: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS WITH PRESET AND CLEAR Description This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the

74ls74a

Abstract: 751A-02
Contextual Info: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

74LS147

Abstract: 74ls147 pin diagram 74ls748 SN54/74LS147,SN54/74LS148 74LS148 motorola 74ls147 PIN 74LS147 74ls147 datasheet 74LS147 equivalent LS148
Contextual Info: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are

Contextual Info: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS W ITH PRESET AND CLEAR Description Pin Configuration This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the

d1410

Abstract: TTL 74LS74 IC 74LS74 74ls74 LC74HC74
Contextual Info: L N al C 7 H 4 6 9 5b c C 7 4 te m o s / V D u a l D - T y p e w i t h F l i p - F l o p R e s e t a n d S e t N d l 695a » LC74HC74 \t D ^ < 7 7>;v7 •CM O SS'Vd^-I^ 7ü-t^ T *$ Ç 7 □ 7 7 L I 'V LS-TO j 74LS74 * § ^ « W f l ï A t f - h' ^ 7 7 7 i< m o ? .n r ^ o

74LS299 APPLICATIONS

Abstract: 74ls74 timing setup hold pin diagram and block diagram of 74ls74 ANSI32
Contextual Info: TMS320SA32 32 KBIT/S ADPCM TRANSCODER NOVEMBER 1986 N PACKAGE ANSI 32 kbit/s ADPCM Compatible TOP VIEW CCITT G.721 32 kbit/s ADPCM Compatible Half-Duplex Transcoder Operation Transmit/Receive Selection Option /t-Law/A-Law PCM Selection Option NC£ 1^ 4 0 □

74ls74a ic

Abstract: SN54L74
Contextual Info: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, 74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR R E V IS E D D E C E M B E R 1983 Package Options Include Both Plástic and Ceram ic Chip Carriers in Addition to Plastic

TMP68661

Contextual Info: TOSHIBA UC/UP S4E D • c]0,ì 7 2 4 Iì G 0 5 4 G 7 5 TO SHIBA Ö24 * T 0 S 3 TM P68661 1. INTRODUCTION - r - is - 3 1 - a n The TMP68661 enhanced program m able communications interface (EPCI) is a universal synchoronous/asynchronous data communications controller chip th at is an

74hc74a

Abstract: plj1 TC74HC74
Contextual Info: - TC74HC74AP/AF/AFN D U A L D - T Y P E F L I P FLOP PRESET A N D C L EA R T h e T C 74H C 74A is a h ig h spe ed CM O S D F L I P F L O P f a b r i c a t e d w i t h s i l i c o n g a t e C 2M O S t e c h n o l o g y . I t a c h i e v e s t h e h i g h s p e e d o p e r a t i o n s i m i l a r to

TC74HC74AP

Abstract: TC74HC74A
Contextual Info: TC74HC74AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC74AP,TC74HC74AF Dual D-Type Flip Flop Preset and Clear The TC74HC74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

Contextual Info: •i TC74HC74AP/AF/AFN D U A L D - T Y P E F L I P FLOP P RE S E T A N D C L E A R T h e T C 7 4 H C 7 4 A is a h ig h speed C M O S D F L I P FLO P fa b r ic a te d w ith s ilic o n g a te C 'M O S te c h n o lo g y . It a ch ie ve s the h igh speed o p e ra tio n

MC2100 REV B

Abstract: MC2100 REV c 74109 MC2100 e rev b MC2100 Rev A MC212 MC2100 MC2300 MC2400 MC2500
Contextual Info: Navigator Motion Processor MC2100 Series Technical Specifications for Brushed Servo Motion Control Performance Motion Devices, Inc. 55 Old Bedford Road Lincoln, MA 01773 Revision 1.6, April 2002 NOTICE This document contains proprietary and confidential information of Performance Motion Devices,

Contextual Info: TC74HCT74AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT74AP,TC74HCT74AF Dual D-Type Flip Flop with Preset and Clear The TC74HCT74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

74hc74a

Abstract: IC 74LS74
Contextual Info: - TC74HC74AP/AF/AFN DUA L D - T Y P E FLIP FLOP PRESET AND CLEAR T h e TC 74H C 74A is a h ig h sp e e d C M O S D F L I P F L O P fa b ric a te d w ith silic o n g a te C2M OS te c h n o lo g y . It a ch iev e s th e h ig h sp eed o p e ra tio n s i m i l a r to

IC 74LS74

Abstract: TC74HC74AP 74LS74 DIP14-P-300-2 TC74HC74AF
Contextual Info: TC74HC74AP/AF 東芝CMOSデジタル集積回路 シリコン モノリシック TC74HC74AP,TC74HC74AF Dual D-Type Flip Flop with Preset and Clear TC74HC74A は､シリコンゲート CMOS 技術を用いた高速 CMOS D タイプフリップフロップです。CMOS の特長である低い消費電力

TC74HC74AFN

Abstract: TC74HC74AP CK1519 74ls74 DIP14-P-300-2 TC74HC74AF
Contextual Info: TC74HC74AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC74AP,TC74HC74AF,TC74HC74AFN Dual D-Type Flip Flop Preset and Clear The TC74HC74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

LDGB

Abstract: AM79C984 PQR100
Contextual Info: PRELIMINARY Am79C984A enhanced Integrated Multiport Repeater eIMR DISTINCTIVE CHARACTERISTICS • Repeater functions comply with IEEE 802.3 Repeater Unit specifications ■ Full LED support for individual port status LEDs and network utilization LEDs

relay VAR 5 6v 5 pin

Abstract: transorb motorola CODEC-SLIC transorb 5V SCHOTTKY DIODE tvs505 equivalent MH88610 MSAN-131 MT8960-67 MT8961 Y6 ZENER DIODE cross reference
Contextual Info: Application Note MSAN-131 Subscriber Line Interface for Digital Switching Systems ISSUE 3 June 1995 Table of Contents 1.0 Introduction • 1.0 Introduction • 2.0 MT8960-67 Voice Codec General Application Information • 3.0 MT8960-67 Functional Description

din 74 AM4

Abstract: IA10 ZEN7103F din+74+AM4
Contextual Info: ＺＥＮ７１０３Ｆ ＶＭＥスレーブボードトランシーバＩＣ Ｚ ＥＮ７１ ０３Ｆ はＶＭ Ｅバス（注１）およびＩ ／Ｏチャ ネルのスレ ーブボー ドで使用 するバス ト ランシーバＩＣです。それぞれの規格に準拠したバスタイミングでマスターボードとデータ転送を行

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

TDA 9345

Abstract: EF9345P IC 74ls74 execution table 3 TDA RGB tv philips TGS0 tda 8035 EF9345 IC 74LS74 datasheet AM11 AM12
Contextual Info: EF9345 HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR . . . . . . . . SINGLE CHIP LOW-COST COLOR CRT CONTROLLER TV STANDARD COMPATIBLE 50Hz or 60Hz 2 SCREEN FORMATS : - 25 (or 21) ROWS OF 40 CHARACTERS - 25 (or 21) ROWS OF 80 CHARACTERS ON-CHIP 128 ALPHANUMERIC AND 128