74LS112A Search Results

74LS112A

Abstract: 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16
Contextual Info: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the

Contextual Info: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE

Contextual Info: MITSUBISHI LSTTLs M 74LS112AP DUAL J-K N EG A TIVE EDGE-TRIGGERED F L IP FLOPS W IT H SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs

74LS112A

Contextual Info: M MOTOROLA SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the

74ls112a

Abstract: SN54/74LS112A SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the

M74LS112AP

Abstract: JK flip flop IC flip flop T Toggle flip flop IC T flip flop IC toggle type flip flop ic M74LS76AP 20-PIN 2V75V
Contextual Info: M IT S U B IS H I LSTTLs M 74LS112AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS W ITH SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs

74LS112A

Contextual Info: M JW 0 T 0 f3 0 1 .X SN54/74LS112A D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 1 1 2 A d u a l J K flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. W h en the c lock goes HIGH, the inputs are enabled and data

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

74LS112AN

Abstract: 74LS112AM
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM 74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary

EATON CM20A

Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
Contextual Info: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid­ ing complete service, fast delivery and in-depth inventory. Our main

54LS112

Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A
Contextual Info: S E M IC O N D U C T O R tm 74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

54s112

Abstract: 74LS112A 74S112
Contextual Info: SN54LS112A, SN54S112, 74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8

LS112A

Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
Contextual Info: SN5 4 L S 112A, SN5 4 S 112, SN7 4 L S 112A, SN7 4 S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 2 A . S N 5 4 S 1 1 2 . . . J OR W P A C K A G E

74LS324

Abstract: 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74C923 equivalent Flip-Flop 7473 74LS324 equivalent 74C08 equivalent
Contextual Info: N T E ELECTRONICS INC 17E H ^3125=1 G0G513S Q B - o S V. ! - TRANSISTOR-TRANSISTOR LOGIC INCLUDES SERIES 74C CMOS NTE TYPE NO. •DESCRIPTION . 7214 7400 74C00 74H00 74LS00 74S00 3-State Sel/Mlpx Quad 2-Input Pos Quad 2-Input Pos Quad 2-Input Pos Quad 2-Input Pos

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) JM38510/07102BEA ACTIVE CDIP

SN74LS112

Abstract: SN54LS112A SN54S112 SN74LS112A SN74S112A SN54L5112A 5S012
Contextual Info: SN54LS112A, SN54S112, SN74 LS112A , SN74 S 112 A D U A L J-K NE GAT IVE EDGE-TRIGGERED FLIP FLO P S WITH PR ESE T AN D CLEA R SDLS011 D 2 6 6 1 , APRIL 1 9 8 2 —REVISED M A R C H 1 9 8 8 • Fully Buffered to Offer Maximum Isolation from External Disturbance

74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Contextual Info: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC

SN74S112

Abstract: LS112A S112 SN54LS112A SN54S112 SN74 SN74LS112A CU12B
Contextual Info: TYPES SN54LS112A, SN54S112, 74LS112A, SN74S112 DUAL J -K NEG ATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR ^ _ Fully Buffered to O ffer M a xim u m Isolation from External Disturbance • R E V IS E D D E C E M B E R 1 9 8 3 S N 5 4 L S 1 1 2 A , S N 5 4 S 1 1 2 . . . J OR W P AC KA G E

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
Contextual Info: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and

UAA2001

Abstract: MC8500 micromodule m68mm19 1N9388 74ALS643 2N6058 MC145026 2N5160 MOTOROLA MC3340 equivalent pn3402
Contextual Info: MOTOROLA Semiconductors THE EUROPEAN MASTER SELECTION 1982 The total num ber of standard Sem iconductor products available from M otorola ex­ ceeds 15 0 0 0 device types. To most of our custom ers this total presents an overw helm ing choice. The European Master Selection lists approxim ately 4 0 0 0 preferred devices that re­

74LS382

Abstract: C1602A C350AVB 74LS08 fan-in 74ls517 74LS556 74LS183 74LS86 full adder MB64H 74LS381
Contextual Info: ix u jD U Lu ra n ctiu F U JIT S U _ mmm CWiOS Gate Array GENERAL INFORMATION The Fujitsu CMOS gate array family consists of twentyeight devlcs types which are fabricated with advanced silicon gate CMOS technology. And more than 14devlc«s are coming. Fujitsu CMOS gate array are configured In a

74LS167

Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
Contextual Info: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.