74F109 Search Results

motorola F74

Abstract: 74F109
Contextual Info: The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop refer to F74 data sheet by connecting the J and K inputs together.

dual d flip-flop

Abstract: t flipflop 74F109
Contextual Info: MOTOROLA DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking_operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D

74f740

Abstract: 74F5074D
Contextual Info: Philip* Semlconductora-Signetic* FAST Producto Product »pacification Synchronizing dual J - K positive edge-triggered flip-flop with metastable immune characteristics FEATURE • Pinout compatible with 74F109 • Metastable immune characteristics • Output skew guaranteed less than 1.5ns

a215c

Abstract: 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: A p riM 9 8 8 Revised January 1999 74F109^ Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to Cp sets Q to LOW level T he F 1 09 consists of tw o high-speed, com pletely indepen­ dent transition clocked JK flip-flops. The clocking operation

74F109

Abstract: 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A
Contextual Info: 54F 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed completely independent transition clocked JK flip-flops The clocking operation is independent of rise and fall times of the clock waveform The JK design allows operation as a D flip-flop refer to ’F74

74F109

Contextual Info: *p n l1 9 , æ Revised January 1999 SEMICONDUCTOR TM 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q sets Q to LOW level The F109 consists of tw o high-speed, com pletely indepen­ den t transition clocked JK flip-flops. The clocking operation

74F109

Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

74F109

Contextual Info: Product specification Philips Semiconductors-Signetics FAST Products Positive J -K positive edge-triggered flip-flops FEATURE TYPE • Industrial temperature range available -40°C to +85°C 74F109 DESCRIPTION The 74F109 is a dual positive edgetriggered JK-type flip-flop featuring in­

8 pin dip j k flipflop ic

Abstract: 74f728 Toggle flip flop IC 74F729 74F109A kO314 74F109 N74F109AD N74F109AN internal diagram of jk flipflop
Contextual Info: FAST 74F109A FLIP-FLOP Synchronizing Dual J-K Positive Edge-Triggered Flip-Flops Preliminary Specification FEATURES • Metastable Immune Characteris­ tics • Same pinout and function as 74F109 • See 74F74A for Synchronizing Dual D-Type Flip-Flop • See 74F728 for Synchronizing

74F109

Abstract: F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild
Contextual Info: Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

schmitt trigger non inverting

Abstract: 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545
Contextual Info: Philips Semiconductors Section 2 FAST TTL Logic Devices FAST TTL Logic Series CONTENTS 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 74F14 74F20 74F27 74F30 74F32 74F37 74F38 74F51 74F64 74F74 74F85 74F86 74F109 74F112 74F113 74F125 74F126

Contextual Info: o o> National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: LOW input to S d sets Q to HIGH level LOW input to C q sets Q to LOW level Clear and Set are independent of clock _ Simultaneous LOW on C q and S q makes both Q and Q

74F109

Contextual Info: Signetics 74F109 FLIP-FLOP Dual J-K Positive Edge-Triggered Flip-Flops FAST Products DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also true and complementary outputs. Set S . and Reset (R ) are asynchronous

74F109

Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: Revised January 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD sets Q to LOW level The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

74F109

Abstract: 74LS245N I74F109D I74F109N N74F109D N74F109N
Contextual Info: Product specification Philips S em ico n d u cto rs-S ig n e tics FAST Products Positive J -K positive edge-triggered flip-flops FEATURE TYPE • Industrial temperature range available -40°C to +85°C 74F109 DESCRIPTION The 74F109 is a dual positive edgetriggered JK-type flip-flop featuring in­

Contextual Info: tß National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The 'F109 consists of two high-speed, completely indepen­ dent transition clocked JR flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

74F109

Contextual Info: 109 54F/74F109 Connection Diagrams Dual JK Positive Edge-Triggered Flip-Flop C d i j_ j Description ,[T T i] vcc * Cd , Jl C d o — is] C K, [ T — O Ki The ’F 1 0 9 j;o n s is ts o f tw o high-speed, com p le te ly independent tra n sitio n clo cked JK flip -flop s. The clo ckin g operation is independent o f rise and

fan 7320

Abstract: fairchild fan 7320 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001
Contextual Info: A p n i1 9 8 8 jgmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm ReVISed N OVem D6T 1 99 9 S E M IC O N D U C T O R TM 74F109_ Dual JK Positive Edge-Triggered Flip-Flop General Description A s y n c h ro n o u s In p u ts : T h e F 1 0 9 c o n s is ts o f tw o _ h ig h -s p e e d , c o m p le te ly in d e p e n ­

74F109

Abstract: I74F109D I74F109N N74F109D N74F109N n74f10
Contextual Info: Philips Semiconductors-Signetics FAST Products Product specification Positive J -K positive edge-triggered flip-flops 74F109 FEATURE TYPE TYPICAL f.« , TYPICAL SUPPLY CURRENT TOTAL • Industrial tem perature range 74F109 125MHz 12.3mA available ( - 4 0 ° C to + 8 5 °C )

KIS-2

Abstract: 74F109
Contextual Info: 109 54F/74F109 Connection Diagrams Dual J K Positive Edge-Triggered Flip-Flop Description The ’ F109 c o n s is ts of tw o high-speed, co m p le te ly in dependent tran sitio n clo ck e d J K flip-flops. The c lo c k in g operation is in dependent o f rise and

74F109

Abstract: I74F109D I74F109N N74F109D N74F109N
Contextual Info: Philips Semiconductors FAST Products Product specification Postive J-K positive edge-triggered flip-flops FEATURE 74F109 PIN CONFIGURATION • Industrial temperature range available –40°C to +85°C RD0 1 16 VCC J0 2 15 RD1 DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop

74F109

Contextual Info: Product specification Philips Semiconductors—Signetics FAST Products Positive J -K positive edge-triggered flip-flops FEATURE TYPE • Industrial temperature range available -40°C to +85°C 74F109 DESCRIPTION The 74F109 is a dual positive edgetriggered JK-type flip-flop featuring in­

74F109

Abstract: I74F109D I74F109N N74F109D N74F109N 74F109DC
Contextual Info: INTEGRATED CIRCUITS 74F109 Positive J-K positive edge-triggered flip-flops Product specification IC15 Data Handbook Philips Semiconductors 1990 Oct 23 Philips Semiconductors Product specification Postive J-K positive edge-triggered flip-flops FEATURE 74F109

74F109

Contextual Info: SN54F109, 74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2932, MARCH 1 9 8 7 - REVISED JANUARY 1989 SN 54F109 . . . J PACKAGE SN 74F109 . . . D OR N PACKAGE Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers,