74ACT11112 Search Results

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET _ SCAS064A - D3339. JUNE 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

T10103

Abstract: 74ACT11112
Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0103—D3339, JUNE 1989— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54 A C T 1 1 1 1 2 . . . J P ACKA G E 7 4 A C T 1 1112 . . . D O R N P ACKA G E

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

74ACT11112

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

TI0103

Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0103— D 3339, JUNE 1989— REVISED JAN U AR Y 1990 • Inputs are TTL-Voltage Compatible 54ACT11112 . . . J PACKAGE 74ACT11112 . . . D OR N PACKAGE Flow-Through Architecture to Optimize PCB

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

74ACT11112DR

Abstract: 74ACT11112N 74ACT11112 74ACT11112D
Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

TI0103

Contextual Info: 54ACT11112, 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 1 0 3 — D 3 3 3 9 • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout C 1 U 1Q C 2 1 PRE IQ • EPIC'“ Enhanced-Performance Implanted

SN49LS704

Abstract: NC-TEX14A-0380 NC-TEX14A SN74HCT38245 sn49ls 74AC11020 SN74BCT38245 sn74s301n TEX39A0380 74AC11132
Contextual Info: TEXAS INSTRUMENTS 1997 Standard Linear and Logic Logic Product Withdrawal Device List June 13 1997 Texas Instruments Semiconductor Group, Standard Linear and Logic, continually monitors worldwide sales and billings activities on all the products offered to

c5088 transistor

Abstract: transistor C3207 TLO84CN sec c5088 IN5355B D2817A C3207 transistor toshiba f630 TLO81CP MC74HC533N
Contextual Info: Transistor - Diode Cross Reference - H.P. Part Numbers to JEDEC Numbers Part Num. 1820-0225 1820-0240 1820-0352 1820-1804 1821-0001 1821-0002 1821-0006 1850-0062 1850-0064 1850-0075 1850-0076 1850-0093 1850-0099 1850-0126 1850-0137 1850-0150 1850-0151 1850-0154