74158 DESCRIPTION Search Results

74157

Abstract: 74158 S1-57 ttl 74157 74s157 pin diagram 74157 pin diagram pin diagram of 74157 pin diagram multiplexer 74157
Contextual Info: 74157, 74158, LS157, LS158, S157, S158 Signetics Data Selectors/Multiplexers '157 Quad 2-Input Data Selector/Multiplexer Non-lnverted '158 Quad 2-Input Data Selector/Multiplexer (Inverted) Product Specification Logic Products DESCRIPTION The '157 is a quad 2-input multiplexer

IC 74157

Abstract: ttl 74157 multiplexer ic 74157 74157 pin diagram pin diagram of 74157 74157 74158 74157 pin configuration pin diagram multiplexer 74157 74157 ic
Contextual Info: 74157, 74158, LS157, LS158, S157, S158 Signetics Data Selectors/Multiplexers '157 Quad 2-Input Data Selector/Multiplexer Non-lnverted '158 Quad 2-Input Data Selector/Multiplexer (Inverted) Product Specification Logic Products DESCRIPTION Th e '1 5 7 is a quad 2-input multiplexer

74157 pin diagram

Abstract: ttl 74157 pin diagram multiplexer 74157 TTL 74158 74157 74158 pin diagram of 74157 74157 pin configuration N74LS157N LS157
Contextual Info: Sjgnetìcs 74157, 74158, LS157, LS158, S157, S158 Data Selectors/Multiplexers '157 Quad 2-Input Data Selector/Multiplexer Non-lnverted '158 Quad 2-Input Data Selector/Multiplexer (Inverted) Product Specification Logic Products DESCRIPTION The '157 is a quad 2-input multiplexer

74157 pin diagram

Abstract: 74LS157 signetics 74s157 pin diagram pin diagram of 74157
Contextual Info: 74157, 74158, LS157, LS158, S157, S158 Signetics Data Selectors/Multiplexers '157 Quad 2-Input Data Selector/Multiplexer Non-lnverted '158 Quad 2-Input Data Selector/Multiplexer (Inverted) Logic Products Product Specification DESCRIPTION The '157 is a quad 2-input m ultiplexer

74157

Abstract: 74158 binary+to+gray+code+conversion+using+ic+74157 74LS157 signetics 74157 pin diagram pin diagram of 74157 74158 pin diagram
Contextual Info: 74157, 74158, LS157, LS158, S157, S158 Signetics Logic Products 1 Data Selectors/Multiplexers DESCRIPTION T h e '1 5 7 is a quad 2-input multiplexer TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL which selects four bits of data from two sources under the control of a com mon

74158

Abstract: 74158 datasheet free download 10VID Vishay 3355 Si7136DP
Contextual Info: SPICE Device Model Si7136DP Vishay Siliconix N-Channel 20-V D-S MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range

74158

Abstract: 74158 datasheet 74158 datasheet free download Si7136DP 74158 description
Contextual Info: SPICE Device Model Si7136DP Vishay Siliconix N-Channel 20-V D-S MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range

7483 4 bit binary full adder

Abstract: 74151 demultiplexer 74153 full adder 74198 shift register 7483 4 bit binary adder 7483 8 bit binary adder 74155 demultiplexer 74150 multiplexer bcd adder with 74283 4 bit 7483 binary adder
Contextual Info: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (MHz) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL 54/7442 BCD-to-Decimal Decoder 22 140 X 54/7443 Excess 3-to-Decimal Decoder 22 X X 54/7444 Excess 3 Gray-to-Decimal Decoder

Contextual Info: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (M H z ) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL DD 54/7442 BC D -to-D e cim al Decoder 22 140 X X 54/7443 Excess 3-to-Decim al Decoder 22 140 X X X 54/7444

TTL 74139

Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Contextual Info: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at

truth table for ic 74138

Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Contextual Info: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture

buffer 74374

Contextual Info: ANALOG DEVICES FEATURES Ultrahigh Speed: Current S ettling to 1 LSB in 35 ns High S tability Buried Zener Reference on Chip M onotonicity Guaranteed Over Tem perature 10.24 mA Full-Scale O utput Suitable for Video Applications Integral and Differential Linearity Guaranteed Over

W29200

Abstract: LT106 ZR2504 74158 free Zyrel zr25 ad5683 IN4*735
Contextual Info: BACK a FEATURES Ultrahigh Speed: Current Settling to 1 LSB in 35 ns High Stability Buried Zener Reference on Chip Monotonicity Guaranteed Over Temperature 10.24 mA Full-Scale Output Suitable for Video Applications Integral and Differential Linearity Guaranteed Over

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 bcd counter using j-k flip flop diagram Multiplexer 74153 CI 74138
Contextual Info: AUGUST 1984 semiconductor MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700, and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors

74158 free

Abstract: LT106 DAC169 74157 pin diagram 74158 datasheet IN4735 AD568 AD568J AD841 AD568K
Contextual Info: a FEATURES Ultrahigh Speed: Current Settling to 1 LSB in 35 ns High Stability Buried Zener Reference on Chip Monotonicity Guaranteed Over Temperature 10.24 mA Full-Scale Output Suitable for Video Applications Integral and Differential Linearity Guaranteed Over

7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
Contextual Info: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
Contextual Info: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74181 74175 clock 74165 block diagram 74151 demultiplexer
Contextual Info: M OIVIOUOUU, s em i c onductor GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700. and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors where each pair is made up of a PMOS and a NMOS transistor.

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

counter 74168

Abstract: 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74151 8 by 1 Multiplexer flip flop 74379 74175 flip flops
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T h is series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 74154 shift register IC sk 7443 full adder circuit using ic 74153 multiplexer DN 74352 full adder using ic 74138 74183 adder pin function of ic 74390 7478 J-K Flip-Flop
Contextual Info: FUJITSU MICROELECTRONICS FUJITSU 37417bH 0010SÔ3 23E D MB65XXXX MB66XXXX MB67XXXX AV CMOS SERÍES GATE ARRAYS ~ June 1986 Edition 2.0 : T - 4 2 - n - o °i DESCRIPTION S The Fujitsu MB65xxxx/MB66xxxx/MB67xxxx family are a series of high performance CMOS gate arrays designed to provide high

74138n

Abstract: buffer 74374 74373 cmos dual s-r latch of IC 74191 G701
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 H 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm a n c e silicon gate 2 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T h is series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/