72205B Search Results

Contextual Info: CMOS PARALLEL SyncFlFO CLOCKED FIFO 256 x 18-BIT, 512 x 18-BIT, 1024 x 18-BIT 2048 X 18-BIT & 4096 X 18-BIT FEATURES: • • • • • • • 256 x 18-bit memory array (72205B) 512 x 18-bit memory array (72215B) 1024 x 18-bit memory array (72225B)

ltsk

Abstract: w5s3
Contextual Info: CMOS PARALLEL SyncFlFO CLOCKED FIFO 256 x 18-BIT, 512 x 18-BIT, 1024 x 18-BIT 2048 x 18-BIT & 4096 x 18-BIT FEATURES: • • • • • • • • • • • • • 256 x 18-bit memory array (72205B) 512 x 18-bit memory array (72215B) 1024 x 18-bit memory array (72225B)

Contextual Info: CMOS PARALLEL SyncFlFO CLOCKED FIFO 256 x 18-BIT, 512 x 18-BIT, 1024 x 18-BIT 2048 x 18-BIT & 4096 x 18-BIT FEATURES: • • • • • • • • • • • • • 256 x 18-bit memory array (72205B) 512 x 18-bit memory array (72215B) 1024 x 18-bit memory array (72225B)

Contextual Info: LH540235/45 FEATURES • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72235B/45B FIFOs • Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal • Device Comes Up into One of Two Known Default

IDT72245LB

Contextual Info: CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096x18 FEATURES: IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB Both FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock WCLK , and a data input enable pin (WEN). Data is read into the synchronous