692858 Search Results

plessey capacitor

Abstract: SL3145C plessey capacitors sine wave inverter using pic BZX79C3V0 SN74123N SP94308
Contextual Info: S e m i M ^ W t o X _ PRELIMINARY INFORMATION SP94308 8-BIT VID EO SYSTEM A D C T h e P lessey S P 9 4 3 0 8 a n a lo g to d ig ita l c o n v e rte r has b een sp e cia lly d e sig n e d fo r use w i t h N T S C o r P A L v i d e o sig n a ls .

EPROM 27128

Abstract: PDSP1601 PDSP1610 PDSP1630 PDSP1640 programmable pipeline microcode memory
Contextual Info: ÊÊk PLESSEY M A R C H 1987 PRELIMINARY INFORMATION S e m ic o n d u c to r s . PDSP1630 PRE-PROGRAMMED SEQUENCER The PDSP1630 is a high speed single chip address sequencer designed to control the execution flow of m icro­ coded instructions. It is optimised to support the Plessey

Contextual Info: M AY 1987 PRELIMINARY INFORMATION SP94308 8-BIT VIDEO SYSTEM ADC The Plessey SP94308 an alo g to d ig ital converter has been specially designed for use w ith NTSC or PAL video signals. A 1V video signal can be AC coupled directly into the device input. The video signal is then

Contextual Info: MARCH 1987 éÊk PLESSE Y PRELIMINARY INFORMATION Semiconductors. MV65030 64-WORD x 9-BIT FIRST-IN FIRST-OUT MEMORY SUPERSEDES SEPTEM BER 1986 E D IT IO N The MV65030 is an asynchronous first-in first-out memory, organised as 64 9-bit words. The device accepts a 9-bit

Contextual Info: A W AUGUST 1987 p l e s s e y PRELIMINARY INFORMATION Sem iconductors. M V 61901 1K WORD x 9-BIT FIRST-IN FIRST-OUT MEMORY SUPERSEDES MAY 1987 EDITION The MV61901 is a dual port RAM that utilises a special First-In, First-Out algorithm that loads and empties data on a

DG28

Abstract: LC28 MV65030 MV66030
Contextual Info: MARCH 1987 PRELIMINARY INFORMATION MV65030 64-WORD X 9-BIT FIRST-IN FIRST-OUT MEMORY SUPERSEDES SEPTEM BER 1986 E D IT IO N The MV65030 is an asynchronous first-in first-out memory, organised as 64 9-bit words. The device accepts a 9-bit parallel word, DO - D8, under control of the shift in (SI) input.

Contextual Info: SEPTEMBER 1988 A F L E S S E Y 'w S e m ico n d u cto rs. ADVANCED INFORMATION P D S P 1 6 4 8 8 SINGLE CHIP 2D CONVOLVER WITH INTEGRAL LINE DELAYS FEATURES FUNCTIONAL DESCRIPTION | Window sizes up to 8 x 8 with a single device • 8 internal line Delays which can be programmed

Contextual Info: APLESSEY W Sem iconductors. MARCH 1987 PRELIMINARY INFORMATION / PDSP1610 MULTIPRECISION MULTI PLIER-ACCUMULATOR SUPERSEDES DECEMBER 1986 EDITION The PDSP1610 is a high speed CMOS Multiply Accumulator with on-chip Register File, Shifter and Feedback Paths that allow DSP algorithms to be executed

MV61901

Abstract: MV65030 MV66030 do-9
Contextual Info: AUGUST 1987 PRELIMINARY INFORMATION MV61901 1K WORD x 9-BIT FIRST-IN FIRST-OUT MEMORY SUPERSEDES M A Y 1987 E D IT IO N The MV61901 is a dual port RAM that utilises a special First-In, First-O ut algorithm that loads and empties data on a first-in, first-out basis. The device provides full and empty

BUS68

Contextual Info: éÊk PLESSEY MARCH 1987 PRELIMINARY INFORMATION Sem iconductors. PDSP1630 PRE-PROGRAMMED SEQUENCER The PDSP1630 is a high speed single chip address sequencer designed to control the execution flow of microcoded instructions. It is optimised to support the Plessey

inverter /U/25/20/maxim max 1987

Abstract: PECON plessey sp ELA60000 692858 ECL IC NAND
Contextual Info: PLESSEY S EM I C O N D U C T O R S T5 9 S m iE ? d ? J Ü X D Ë | 72SDS13 Q D D ? m -f- ÿ 2 ~ / / ~ / 3 S | _ _ a u g u s t 1987 ELA 60000 SERIES ECL GATE ARRAYS SUPERSEDES NOVEMBER 1986 AND APRIL 1987 EDITIONS The ELA60000 series of ECL gate arrays is a