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Contextual Info: N N 5 1 V 1 6 1 6 5 A / N N 5 1 V 1 8 1 6 5 A E D O s e r ie s H y p e r P a g e M o d e C M O S 1M x x N P N w i W l 1 6 b it D y n a m ic R A M Preliminary Specification d e s c rip tio n The NN51V16165A/18165A series is a high performance CMOS Dynamic Random Access Memory orga­