64X18 Search Results

SN74ACT7804

Abstract: SN74ACT7806 SN74ACT7814 64X18
Contextual Info: SN74ACT7814 64x18 STROBED FIRST-IN, FIRST-OUT MEMORY S C A S 2 0 9 A -A P R IL 1 9 9 2 - R EVISED SEPTE M B E R 1995 Member of the Texas Instruments Widebus Family DL PACKAGE TOP VIEW Load Clock and Unload Clock Can Be Asynchronous or Coincident RESET [ 1

Contextual Info: SN74ACT781 4 64x18 STROBED FIRST-IN, FIRST-OUT M EM OR Y S C AS 209A - APRIL 1992 - REVISED SEPTEMBER 1995 M e m b e r of the Te x a s I n s t r u m e n t s W i d e b u s Fa mi l y DL PACKAGE TO P V IE W Load Cl o c k and Unl oa d Cl ock Can Be A s y n c h r o n o u s or C o i n c i d e n t

ad 161

Abstract: vhdl code PN code generator ad 152 transistor ad 153 transistor S-108 PF144 PQ208 QL5130 QL5130-33APF144C QL5130-33APQ208C
Contextual Info: QL5130 - QuickPCITM 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM last updated 12/1099 Device Highlights DEVICE HIGHLIGHTS Q8DÃ7ˆ†Ã±Ã""ÃHC“Ã"!Ãiv‡†Ãqh‡hÃhqÃhqq…r†† High Performance PCI Controller • 32-bit / 33 MHz PCI Target

SN74ACT7803

Abstract: SN74ACT7805 SN74ACT7813 SN74ALVC7803 SN74ALVC7805 SN74ALVC7813
Contextual Info: SN74ALVC7803, SN74ALVC7805, SN74ALVC7813 512x 18, 256x 18, 64x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS436 - JUNE 1994 DL PACKAGE TOP VIEW Free-Running Read and Write Clocks Can Be Asynchronous or Coincident RESET D17 D16 D15 D14 D13 D12 D11 Read and Write Operations Synchronized to

Contextual Info: Aluminum Electrolytic Capacitors Large Can Type GUP Series GUP Series Features • High C V value with expanded case size <>64 x 103 - <|>90 x 221 ■ High ripple current (approx. 1 . 5 - 2 times of GYU-series) Specifications Item Performance Characteristics

verilog code for slave SPI with FPGA

Abstract: XC3S50 XC2V80
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

QL5332-33APQ208C

Abstract: 1.9 TDI Schematic PB256 PCI32 PQ208 QL5032 QL5332 PCI32N AD1892
Contextual Info: QL5332 - Enhanced QuickPCITM Device 33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM last updated 2/5/01 QL5332 - Enhanced QL5032 • ■ ■ ■ ■ ■ ■ PCI Bus – 33 MHz 32 bits data and address Supports all PCI commands (including configuration

ST CHN t4

Contextual Info: QL5064 QuickPCI Data Sheet •••••• 66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller • 64-bit/66 MHz Master/Target PCI Controller automatically backwards compatible to 33 MHz

Contextual Info: QL5064 QuickPCI Data Sheet •••••• 66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller • 64-bit/66 MHz Master/Target PCI Controller automatically backwards compatible to 33 MHz

Contextual Info: Am 29332 32-Bit Arithmetic Logic Unit • Single Chip, 32-Bit ALU Supports 8 0 -9 0 ns m icrocycle tim e fo r the 32-bit data path. It is a com binatorial ALU with equal cy­ cle tim e fo r all instructions. Flow -through A rchitecture A com binatorial ALU with tw o input data ports and

67417J

Abstract: 128X9 PIS01 serial input parallel output
Contextual Info: Serializing First-In-First-O ut FIFO 6 4 x 8 /9 Memory Features/ Benefits • High-speed 28-MHz serial shift-ln/shift-out rate • 10-MHz parallel shift-in/shift-out rate • Three-state outputs with Hi-current drive 67417 Ordering Information PART NUMBER

Contextual Info: Order this data sheet by H4C/D MOTOROLA H SEMICONDUCTOR “ TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H P ER FO R M A NC E T R IP L E LAYER M ETAL S U B -M IC R O N CMOS ARRAYS The s u b -m ic ro n H 4C S e rie s ’ " CM OS gate array fa m ily and th e new

PF144

Abstract: QL5030
Contextual Info: Back QL5030 - QuickPCI ESP 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Advance Data DEVICE HIGHLIGHTS Updated: 22-Feb-99 High Performance PCI Controller - 32-bit / 33 MHz PCI Target PCI Zero-wait state PCI Target provides 132 MB/s transfer rates

Contextual Info: a CtT7A i T O ' 41 Serializing First-In First-Out (FIFO 64 x 8/9 Memory Features/Benefits • High-speed 28-MHz serial shlft-ln/shilt-out rate Advanced Micro Devices Ordering Information • 10-MHz parallel shlit-ln/shlft-out rate Part Number Package Temp

Contextual Info: 大型铝电解电容器 LSG LARGE CAN TYPE ALUMINUM ELECTROLYTIC CAPACITORS 系列 LSG SERIES 螺栓端子型105℃ 5000小时品 105℃ 5000 hours, Screw Terminal Type ◆特 长／FEATURES • 105℃5000小时品。 • RoHS指令对应品。 Load Life : 105℃ 5000 hours.

Contextual Info: LSG LARGE CAN TYPE ALUMINUM ELECTROLYTIC CAPACITORS LSG SERIES 105℃ 5000 hours, Screw Terminal Type ◆FEATURES ・Load Life : 105℃ 5000 hours. ・RoHS compliance. ◆SPECIFICATIONS Items Characteristics Category Temperature Range −25~＋105℃ Rated Voltage Range

hct 4047 bt

Abstract: SN74ALS679 FCT Fast CMOS TTL Logic 74LS 4075 7804 inverter SN74368A DTL Logic 4069 CMOS hex inverter SN502 CD74AC374
Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

74HCT 4013

Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Contextual Info: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

PF144

Abstract: QL5030 QL5030-33APF144C TQ144
Contextual Info: QL5030 QuickPCI Data Sheet • • • • • • 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM 1.0 Device Highlights High Performance PCI Controller • Programmable Interrupt Generator • I2O Support with Local Processor

450WV

Contextual Info: 大形アルミニウム電解コンデンサ LSG LARGE CAN TYPE ALUMINUM ELECTROLYTIC CAPACITORS LSG シリーズ SERIES ネジ端子形105℃標準品 105℃ Standard, Screw Terminal Type ◆特 長／FEATURES ・RoHS指令対応品。 RoHS compliance.

M2GL005

Abstract: db hpms
Contextual Info: Revision 0 IGLOO2 FPGAs Introduction Microsemi’s IGLOO 2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable, and the most secure programmable logic solution. This next generation IGLOO2

QL5130-33APF144C

Abstract: QL5130 QL5130-33APQ208C QL5130-33APQ
Contextual Info: QL5130 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller Programmable Logic • 57 K system gates/619 logic cells • 13,824 RAM bits, up to 157 I/O pins

Contextual Info: QL5030 - QuickPCI ESP 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Advance Data D e v ic e H ig h l ig h t s Updated: 1-Apr-99 5 High Performance PCI Controller - 32-bit / 33 M Hz PCI Target PCI Zero-wait state PCI Target provides 132 MB/s transfer rates

MCR 22-8 transistor power

Abstract: Transistor motorola 418 10146 1987 carrier A022H on 5295 equivalents HDC031 Mustang 300 HDC011 HDC016 HDC049
Contextual Info: Order this data sheet by HDC/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA HIGH PERFORMANCE TRIPLE LAYER METAL HDC SERIES CMOS ARRAYS 1.0 MICRON CMOS ARRAYS Built on a 1.0 micron, triple-layer metal CMOS process, the HDC Series represents a significant advancement in microchip technology.