6 PIN HX Search Results

Contextual Info: ADVANCE M IC R O N 16 MEG X MT8D168 8 DRAM M OD ULE 16 MEG x 8 DRAM FAST PAGE MODE FEATURES PIN ASSIGNMENT Top View OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7 • Packages Leadless 3 0 -pin SIMM Leaded 30-pin SIP 30-Pin SIMM (T-6)

Contextual Info: PCA9561 Quad 6-bit multiplexed I2C-bus EEPROM DIP switch Rev. 4 — 6 November 2012 Product data sheet 1. General description The PCA9561 is a 20-pin CMOS device consisting of four 6-bit non-volatile EEPROM registers, six hardware pin inputs and a 6-bit multiplexed output. It is used for DIP

cey marking code

Abstract: 816P
Contextual Info: SHARP L H 5 3 1 6 P 0 ODD C O N T E N T S 1. General Description P2 2. Features P2 3. Block Diagraa P3 4. Pin Connections P4 5. Pin Description P4 6. Absolute ïaiinna Ratings PS 7. Opwatine Sanges P5 S. B.C. Electrical Characteristics P5 9. À.C. Electrical Characteristics

xnor cmos

Abstract: DS1012Z DS1012 DS1012M 1040d1
Contextual Info: DS1012 DS1012 2-in-1 Sub-Miniature Silicon Delay Line with Logic FEATURES PIN ASSIGNMENT • All-silicon time delay • 53 µW max. CMOS quiescent mode • Surface mount 8-pin mini-SOIC and standard 8-pin DIP 1 8 VCC 2 7 IN2 OUT1 3 6 OUT2 GND 4 5 OUT4 DS1012M 8-PIN DIP 300 MIL

DS1012

Abstract: DS1012M DS1012Z 1040d1
Contextual Info: DS1012 DS1012 2-in-1 Sub-Miniature Silicon Delay Line with Logic FEATURES PIN ASSIGNMENT • All-silicon time delay • 53 µW max. CMOS quiescent mode • Surface mount 8-pin mini-SOIC and standard 8-pin DIP 1 8 VCC 2 7 IN2 OUT1 3 6 OUT2 GND 4 5 OUT4 DS1012M 8-PIN DIP 300 MIL

Contextual Info: HXILINX XC95108 In-System Programmable CPLD June 1,1 9 9 6 Version 1.0 Preliminary Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins foNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins

Contextual Info: DS1012 DS1012 2-in-1 Sub-Miniature Silicon Delay Line with Logic DALLAS SEMICONDUCTOR FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 C 1 8 : Vcc OU TaC OUT1 £ 2 7 : IN2 • Surface mount 8-pin mini-SOIC and standard 8-pin DIP 3 6 GNDC 4 5 • 2 independent buffered delays per input

MLV-10-4R-6G

Contextual Info: M LV -10-4R -6G BAR GRAPH ARRAY ^^3T C =I Pin No. 20 19 18 17 16 15 14 13 12 11 Pin No. 6 d=J n □ 0 . 20 ( 0 . 31 ) 1 2 3 4 5 7 8 9 10 (0.40) Pin ~Jj No.20 I] Pin No.! Unit : mm (inch) I 7.7 (0.30) RED 40 60 15 0.18 5 ABSOLUTE MAXIMUM RATINGS (Ta=25°C)

Contextual Info: MITSUBISHI LSIs M5M2 7C256K, -2, -3 2 6 2 1 4 4 - B IT 3 2 7 6 8 - W ORD BY 8 -B IT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The Mitsubishi M 5 M 2 7 C 2 5 6 K is a high-speed 2 6 2 1 4 4 -b it ultraviolet erasable and electrically reprogrammable read

Contextual Info: M LV -10-4R -6G BAR GRAPH ARRAY ^^3T C =I ~a~ d=J n □ 5 .0 Pin No. 20 19 18 17 16 15 14 13 12 11 Pin No. 6 O.Z 1.0 0 . 20 ( 0 .0 3 ) (0 .3 1 ) to .t o 1 2 3 4 5 7 8 9 10 ( 0 .4 0 ) Pin Tj Pin N o .2 0 11 No. 1 I Unit : mm (inch) 7.7 (0 .3 0 ) ABSOLUTE MAXIMUM RATINGS (Ta=25°C)

Contextual Info: CELESTICA, 16M x 32 EDO SIMM FEATURES • . 72-pin industry standard four-byte single-in-line memory module JEDEC compliant: 21-C, Fig. 4-6 Release 6 No. 95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS Single 3.3 ± 0.3V power supply

CL001D16325B00J-60

Contextual Info: CELESTICA, 16M x 32 EDO SIMM FEATURES 72-pin industry standard four-byte single-in-line memory module JEDEC compliant: 21-C, Fig. 4-6, 4-18 Release 6 No. 95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS Single 5.0V ± 10% power supply

ebl41

Abstract: DS1228S DS1867 ordering information DS1669 Digital Pot IC DS1640
Contextual Info: DALLAS SEMICONDUCTOR FEATURES DS1806 Digital Sextet Potentiom eter PIN ASSIGNMENT • Six digitally controlled 6 4 -position potentiom eters 1 20 □ W2 C 2 19 □ H1 L1-3 C 3 18 □ H2 4 17 5 16 □ □ H3 W4 C C L4-6 C 6 15 □ H5 W6 C 7 14 □ W5 D S 1806-010 - 10K ohm

100-20L

Abstract: b711 DS1666 DS2011D part 100-20L 20-PIN DS1806 DS1806-010 DS1806-050 DS1806E
Contextual Info: DALLAS SEMICONDUCTOR FEATURES DS1806 Digital Sextet Potentiom eter PIN ASSIGNMENT • Six digitally controlled 6 4 -position potentiom eters 1 20 □ W2 C 2 19 □ H1 L1-3 C 3 18 □ H2 4 17 5 16 □ □ H3 W4 C C L4-6 C 6 15 □ H5 W6 C 7 14 □ W5 D S 1806-010 - 10K ohm

Contextual Info: MITSUBISHI < DIGITAL ASSP> M66230P/FP AaRT ADVANCED ASYNCHRONOUS RECEIVER & TR ANSM ITTER DESCRIPTION T h e M 6 6 2 3 0 P /F P is an in teg ra te d circuit lo r asynchronous PIN CONFIGURATION (TOP VIEW) serial data com m unications.lt is used in com bination with an

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

PA9539RPW

Abstract: transistor SMD n17 transistor SMD N02
Contextual Info: PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 6 — 6 February 2013 Product data sheet 1. General description The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output GPIO expansion with interrupt and reset for

Contextual Info: ^ CELESTICA- 2M x 32 FPM SIMM FEATURES • • 72-pin industry standard 4-byte single-in-line memory module JED EC compliant: 21-C, Fig. 4-18 A,B. Fig- 4-6 Release 6 No.95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS Single 5V ± 10% power supply

14523C

Contextual Info: CELESTICA 1M x 36 PTY FPM SIMM FEATURES • • • 72-pin industry standard 4-byte single-in-line memory module JEDEC compliant: 21 -C, Figure 4-6, 4-18 A,B Release 6 ; No.95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS Single 5V ± 10% power supply

Contextual Info: PCA9538 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 6 — 6 February 2013 Product data sheet 1. General description The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallel Input/Output GPIO expansion with interrupt and reset for I2C-bus/SMBus applications

20571C

Contextual Info: ^ CELESTICA 1M x 32 FPM SIMM FEATURES • • • 72-pin industry standard 4-byte single-in-line memory module JEDEC compliant: 21-C, Fig. 4-18 A,B, Fig. 4-6 Release 6 No.95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS Single 5V ± 10% power supply

Contextual Info: CELESTICA 1M x 32 EDO SIMM FEATURES • • • • • • • • • 72-pin industry standard 4-byte single-in-line memory module JEDEC compliant: 21-C, Fig. 4-18 A,B, Fig. 4-6 Release 6 No. 95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS

edo simm

Abstract: 5857C
Contextual Info: CELESTICA 1M x 32 EDO SIMM FEATURES • • • 72-pin industry standard four-byte single-in-line memory module JEDEC compliant: 21-C, Fig. 4-18 A,B, Fig. 4-6 Release 6 ; No.95 MO-116 Supports 90°, 40° and 22.5° connectors High performance, CMOS Single 5V ± 10% power supply

Contextual Info: M IT S U B IS H I L S I s M 5 M 4 V preu 4 2 8 J , T P , R T - 6 , - 7 , - 8 , - 6 S , - 7 S , - 8 S FAST PAGE MODE 4718592-BIT 262144-WORD BY 18-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a fam ily o f 2 6 2 1 4 4 -w o rd by 18-bit dynam ic RAM s,