5FIBFL45B Search Results

OTP-e

Abstract: TEMIC NEC protocol
Contextual Info: ' • SôbôMSb 00übD32 EI D WM T e m ic TSS461C Semiconductors Vehicle Area Network Data Link Controller 1. Description Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the use of more advanced and intelligent electronic circuits.

ITT 435-1

Contextual Info: S iW H S electronic June 1992 HM 65798 HI-REL DATA SHEET_ 64 k x 4 HIGH SPEED CMOS SRAM FEATURES . TTL COMPATIBLE INPUTS AND OUTPUTS • FAST ACCESS TIME : 25*/35/45/55 ns . LOW POWER CONSUMPTION ACTIVE: 660 mW STANDBY : 190 mW . WIDE TEMPERATURE RANGE : - 55°C TO + 125°C

1553 bus

Abstract: HM-65664 80C31M
Contextual Info: 5öbß45b QÜ0E3M3 1ÖT • MMHS January 1991 Preview MATRA H H S 29C530 HI-REL DATA SHEET MIL-STD-1553B PROTOCOL MANAGEMENT UNIT FEATURES . PIN PROGRAMMABLE FEATURES : - COMPATIBILITY WITH INTEL AND MOTOROLA MICROPROCESSORS - 8 OR 16 BIT INTERFACE - SUPPORT OF THREE MEMORY INTERFACE

Shared resource arbitration

Contextual Info: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE

MHS CMS

Contextual Info: C TSC8051A30 S e m i c o n d u c t o r s CMOS Single Chip 8-bit Microcontroller with VAN Controller Description The TSC8051A30 is a stand alone, high performance CMOS microcontroller designed for use in automotive and industrial applications. The TSC8051A30 retains all features o f the MHS 80C51

Contextual Info: Tem ic 29C532E Semiconductors 32-Bit Bus-Watch EDAC Error Detection And Correction unit 1. Description The 29C532E EDAC is a very low power bus-watch 32-bit Error Detection And Correction unit EDAC . EDAC is used in a high integrity system for monitoring

Contextual Info: Tem ic 29C93A MATRA MHS ECMA102/V110 Terminal Rate Adaptor Circuit TRAC Description The 29C93A is a Terminal Rate Adaptor Circuit (TRAC) performing speed adaptation between synchronous/asynchronous V24 terminals through ISDN 64 kbps “B” channel. The TRAC can be connected to “B” channel using a

67130V

Abstract: ajr38 a9lc
Contextual Info: IlM l L 67130/L 67140 DATA SHEET 1Kx8 CMOS DUAL PORT RAM 3.3 Volt FEATURES . SINGLE 3.3 V ±0.3 VOLT POWER SUPPLY . FAST ACCESS TIME 45 NS * TO 70 NS . 67130L/67140L LOW POWER 67130V/67140V VERY LOW POWER . EXPANDABLE DATA BUS T 0 16 BITS OR MORE USING MASTER/SLAVE DEVICES WHEN USING

MCT12K

Abstract: MC10K
Contextual Info: T em ic Arrays: MG1RT S e m i c o n d u c t o r s Radiation-Tolerant 0.6- |xm CMOS Sea-of-Gates Description TEMIC/Matra MHS is the first European supplier for space application submicronic radiation tolerant CMOS ASICs. This is why TEMIC keeps offering a wide range of quality

Contextual Info: Tem ic TSC8051A2 S e m i c o n d u c t o r s CMOS Single Chip 8-bit Microcontroller with Analog Interfaces Description The TSC8051A2 is a stand alone, high performance CMOS microcontroller designed for use in automotive and industrial applications. The TSC8051A2 retains all features of the 80C51 with

MB-7500

Abstract: 130 nm CMOS standard cell library ST
Contextual Info: Mrüll electronic June 1992 ASIC HI-REL DATA SHEET MB GATE ARRAY SERIES - 2\U2 METAL LAYERS MB 850 - MB 1300 - MB 2000 - MB 2700 - MB 3200 MB 4000 - MB 5000 - MB 6600 - MB 7500 FEATURES ADVANCED SILICON GATE CMOS PROCESS : - two metal level - 2 micron drawn channel length

Contextual Info: Hm m electronic June 1992 M 67201 HI-REL DATA SHEET_ 512x9 CMOS PARALLEL FIFO FEATURES FIRST-IN FIRST-OUT DUAL PORT MEMORY . EMPTY, FULL AND HALF FLAGS IN SINGLE DEVICE MODE WIDE TEMPERATURE RANGE : - 55°C TO + 125°C . RETRANSMIT CAPABILITY . BI-DIRECTIONAL APPLICATIONS

mxt 211

Contextual Info: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or El-CEPT transceivers. The 29C96 supports following frame formats : • DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)

mhs 80C32

Contextual Info: 4bE D SfiböHSb 00002bñ 1 September 1989 matra M H S 80C52/80< DATA SHEET CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C52 - CMOS SINGLE -CHIP 8 BIT MICRO­ CONTROLLER with factory m ask-programmable ROM 80C52/C32 : 0 to 12 MHz 80C52-1/C32-1 : 0 to 16 MHz 80C52S/C32S : 0 to 20 MHz

transistor A6I

Contextual Info: MHS electronic June 1992 HM 65262 HI-REL DATA SHEET_ 16 k x 1 VERY LOW POWER CMOS SRAM FEATURES ACCESS TIME : 70/85 ns . TTL COMPATIBLE INPUTS AND OUTPUTS VERY LOW POWER CONSUMPTION ACTIVE :1 10 mW typ STANDBY : 2.0 uW (typ) DATA RETENTION : 0.8 uW (typ)

Contextual Info: Tem ic M 67203/M 67204 MATRA MHS 2K x 9 & 4K x 9 CMOS Parallel FIFO Introduction The M67203/204 implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word