555C Search Results

D2784

Abstract: 555i TLC555C TLC555M
Contextual Info: TLC555M, TLC555I, 555C LinCMOS TIMERS D2784, SEPTEMBER 1983-REVISED OCTOBER 1988 Very Low Power Consumption . . . 1 mW Typ at V q d • 5 V TLC 555M . . . JG PACKAGE TLC 555I, TLC 555C . . . D OR P PACKAGE TOP VIEW Capable of Operation in Astable Mode

HN58C256ATI-85

Contextual Info: HN58C256AI Series 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM HITACHI ADE-203-555C Z Rev. 3.0 Sep. 5, 1997 Description The Hitachi HN58C256AI is a electrically erasable and programmable ROM organized as 32768-word x 8bit. It has realized high speed low power consumption and high reliability by employing advanced MNOS

I5555

Contextual Info: HN58C256AI Series 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM HITACHI ADE-203-555C Z Rev. 3.0 Sep. 5, 1997 Description The Hitachi HN58C256AI is a electrically erasable and programmable ROM organized as 32768-word X 8bit. It has realized high speed low pow er consumption and high reliability by employing advanced MNOS

Hitachi DSAUTAZ006

Contextual Info: HN58C256AI Series 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-555C Z Rev. 3.0 Sep. 5, 1997 Description The Hitachi HN58C256AI is a electrically erasable and programmable ROM organized as 32768-word × 8bit. It has realized high speed low power consumption and high reliability by employing advanced MNOS

HN58C256AI

Abstract: HN58C256ATI-85 Hitachi DSA00164
Contextual Info: HN58C256AI Series 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-555C Z Rev. 3.0 Sep. 5, 1997 Description The Hitachi HN58C256AI is a electrically erasable and programmable ROM organized as 32768-word × 8bit. It has realized high speed low power consumption and high reliability by employing advanced MNOS

SG555

Contextual Info: Timer S G 555/S G 555C The SG 5 5 5 integrated circu it has been designed to generate accurate tim e delays w ith provisions for remote triggering or re­ setting. An external resistor and capacitor w ill provide precise control of tim e delays from m icroseconds to hours. T h is circu it

HN58C256ATI-85

Abstract: HN58C256AFPI-10 HN58C256AFPI-85 HN58C256AI HN58C256ATI-10 Hitachi DSA0047
Contextual Info: HN58C256AI Series 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-555C Z Rev. 3.0 Sep. 5, 1997 Description The Hitachi HN58C256AI is a electrically erasable and programmable ROM organized as 32768-word × 8bit. It has realized high speed low power consumption and high reliability by employing advanced MNOS

Contextual Info: DGN-8 D-8 THS4502-EP THS4503-EP www.ti.com SGLS291 − APRIL 2005 WIDEBAND, LOWĆDISTORTION FULLY DIFFERENTIAL AMPLIFIERS FEATURES D Controlled Baseline D One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −555C D D D D D

Contextual Info: NL17SZ86 Single 2-Input Exclusive-OR Gate The NL17SZ86 is a high performance single 2−input Exclusive−OR Gate operating from a 2.3 V to 5.5 V supply. http://onsemi.com Features • • • • • • • • • • Extremely High Speed: tPD 2.4 ns typical at VCC = 5.0 V

523AN

Abstract: PCA9306 PCA9306DTR2G UDFN-8 PCA9306USG
Contextual Info: PCA9306 Dual Bidirectional I2C-bus and SMBus Voltage-Level Translator The PCA9306 is a dual bidirectional I2C−bus and SMBus voltage−level translator with an enable EN input. http://onsemi.com Features MARKING DIAGRAMS • 2−bit Bidirectional Translator for SDA and SCL Lines in

613AF

Abstract: uDFN-6
Contextual Info: NLU1GT86 Single 2-Input Exclusive OR Gate, TTL Level LSTTL−Compatible Inputs The NLU1GT86 MiniGatet is an advanced CMOS high−speed 2−input Exclusive OR gate in ultra−small footprint. The device input is compatible with TTL−type input thresholds and

MC74VHC1G32DFT1G

Abstract: SOt23-5 footprint wave soldering
Contextual Info: MC74VHC1G32 Single 2-Input OR Gate The MC74VHC1G32 is an advanced high speed CMOS 2−input OR gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output.

MC74VHC1G08DFT2G

Abstract: V2MG MC74VHC1G08DFT1G MC74VHC1G0 MC74VHC1G08
Contextual Info: MC74VHC1G08 Single 2-Input AND Gate The MC74VHC1G08 is an advanced high speed CMOS 2−input AND gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output.

sot-353 he Inverter

Abstract: SOT-353 MARKING L5 tr marking code l5 marking nc sot-353
Contextual Info: NL17SZ04 Single Inverter The NL17SZ04 is an inverter in two tiny footprint packages. The device performs much as LCX multi−gate products in speed and drive. Features • • • • • • • • Tiny SOT−353 and SOT−553 Packages 24 mA Sink and Source Output Capability

Contextual Info: INA321 INA2321 SBOS168C − DECEMBER 2000 − REVISED MARCH 2005 microPower, Single-Supply, CMOS Instrumentation Amplifier FEATURES APPLICATIONS D LOW QUIESCENT CURRENT: 40µA/channel D INDUSTRIAL SENSOR AMPLIFIERS: D D D D D D D D D Shut Down: < 1µA HIGH GAIN ACCURACY: G = 5, 0.02%,

Contextual Info: LMC555 www.ti.com SNAS558J – FEBRUARY 2000 – REVISED MARCH 2013 LMC555 CMOS Timer Check for Samples: LMC555 FEATURES 1 • 2 • • • • • • • • • Less than 1 mW Typical Power Dissipation at 5V Supply 3 MHz Astable Frequency Capability 1.5V Supply Operating Voltage Ensured

Contextual Info: TPS76815ĆEP, TPS76818ĆEP, TPS76825ĆEP, TPS76827ĆEP TPS76828ĆEP, TPS76830ĆEP TPS76833ĆEP, TPS76850ĆEP, TPS76801ĆEP FASTĆTRANSIENTĆRESPONSE 1ĆA LOWĆDROPOUT VOLTAGE REGULATORS SGLS011B − MARCH 2003 − REVISED DECEMBER 2008 FEATURES D 1−A Low-Dropout Voltage Regulator

UC2825A-EP

Abstract: UC2825 UC2825A UC2825AMDWREP UC2825AQDWREP UC3823A SLUA125 UC2825a-q1 UC2825AQEP UDG-95109
Contextual Info: UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 HIGH-SPEED PWM CONTROLLER Check for Samples: UC2825A-EP FEATURES 1 • • • • • • • • • Improved Version of the UC2825 PWM Compatible With Voltage-Mode or Current-Mode Control Methods

555C

Abstract: NLAS9431 NLAS9431MTR2G WQFN16 WQFN-16
Contextual Info: NLAS9431 Low Voltage Single Supply Dual DPDT Analog Switch The NLAS9431 is an advanced dual−independent CMOS double pole−double throw DPDT analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining CMOS low power

555C

Abstract: NLAST9431 NLAST9431MTR2G WQFN16 WQFN-16
Contextual Info: NLAST9431 Low Voltage Single Supply Dual DPDT Analog Switch The NLAST9431 is an advanced CMOS dual−independent DPDT double pole−double throw analog switch, fabricated with silicon gate CMOS technology. It achieves high−speed propagation delays and low ON resistances while maintaining CMOS low−power

ca555

Abstract: CA555C LIMING RELAY LM555C MC1555 harris SE555 CA555 DIP MC1455 NE555 SE555
Contextual Info: HA R R I S S E M I C O N D S E C T O R 4GE D • M 3 0 2 2 7 1 D D 3 S 3 3 4 7 ■ HAS T 1 } H a r r i s C A 5 5 5 , C L A M 5 5 5 5 C 5 5 C , * Timers For Timing Delays & Oscillator Applications in Commercial, Industrial & Military Equipment August 1991 Features

LX MARKING SC70-5

Abstract: cw186 NL17SZ17DFT2G NL17SZ17DFT2 A114 A115 C101 JESD22 NL17SZ17
Contextual Info: NL17SZ17 Single Non-Inverting Buffer with Schmitt Trigger The NL17SZ17 is a single Non−inverting Schmitt Trigger Buffer in two tiny footprint packages. The device performs much as LCX multi−gate products in speed and drive. http://onsemi.com Features •

A114

Abstract: A115 C101 JESD22
Contextual Info: 7WB383 Bus Exchange Switch The 7WB383 is an advanced high−speed low−power bus exchange switch in ultra−small footprints. Features • • • • • • • High Speed: tPD = 0.25 ns Max @ VCC = 4.5 V 3 W Switch Connection Between 2 Ports Power Down Protection Provided on Inputs

A114

Abstract: A115 C101 JESD22
Contextual Info: 7WB3125 2-Bit Bus Switch The 7WB3125 is an advanced high−speed low−power 2−bit bus switch in ultra−small footprints. Features • • • • • • • High Speed: tPD = 0.25 ns Max @ VCC = 4.5 V 3 W Switch Connection Between 2 Ports Power Down Protection Provided on Inputs