54LS125AFM Search Results

Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers General Description cant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the

74LS125APC

Abstract: 74LS125AP 74LS125AFC
Contextual Info: ! NATIONAL SENICOND {LOGIC} D5E D I t.SG1125 00^3003 □ I T -m s- ¿5 .fé CO NN ECTIO N DIAGRAM PINOUT A 54/74125 54LS/74LS125A QUAD BUS BUFFER GATE With 3-State Outputs ORDERING CODE: See Section 9 PIN PKGS COM MERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%,

74LS125APC

Abstract: 74LS125AP 74125 74LS125ADC 54*125 54125DM 54125FM 54LS125ADM 54LS125AFM 74125DC
Contextual Info: 125 C O N N E C T IO N D IA G R A M P IN O U T A 54/74125 Z>15 'V54LS/74LS125A QUAD BUS BUFFER GATE With 3-S ta te Outputs O R D E R IN G C O D E: See S e c tio n 9 PIN PKG S OUT C O M M E R C IA L G RADE M ILITA R Y G RADE V c c = +5.0 V ±5%, T a = 0 ° C to + 7 0 “ C

U1221

Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers This device contains fo u r independent gates each of which perform s a non-inverting buffer function. The outputs have the 3-STATE feature. W hen enabled, the outputs exhibit the low im pedance characteristics o f a standard LS output with

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AW DM74LS125AM DM74LS125AN E20A J14A
Contextual Info: NATIONAL SENICOND -CLOGIO 31E D bSGliaa QGbTöbB 3 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description that two outputs will attempt to take a common bus to oppo­ site logic levels, the disable time Is shorter than the enable time of the outputs.

54LS125

Abstract: 54LS125A 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125A DM54LS125AJ DM54LS125AW DM74LS125A DM74LS125AM
Contextual Info: 54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output

74LS125APC

Contextual Info: 125 CO NNECTIO N DIAGRAM PINOUT A 54/74125 c, f 0 <5<4 >v54LS/74LS125A ^ Q U A D BUS BUFFER G A TE (W ith 3 -S ta te O u tp u ts ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, T a = 0 °C to +70° C V cc = +5.0 V ±10%,

DM74LS125A

Abstract: DM54LS125AW DM74LS125AM DM74LS125AN 54LS125 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ
Contextual Info: DM74LS125A Quad 3-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with

JX - 638

Abstract: 54LS125A
Contextual Info: June 1989 5 4 L S 12 5A /D M 5 4L S 12 5A /D M 74 L S 1 25 A Quad TR I-STA TE B uffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125A DM74LS125AM DM74LS125AN E20A
Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers cant load nor as a driver. To m inim ize th e possibility th a t two outputs will attem pt to ta ke a com m on bus to opposite logic levels, th e disable tim e is shorter than the enable tim e of the

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125AM DM74LS125AN E20A
Contextual Info: June 1989 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description This device contains lour independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

54LS125ADMQB

Abstract: 54LS125AFMQB 54LS125ALMQB DM54LS125AW DM74LS125AM DM74LS125AN E20A J14A 54LS125
Contextual Info: LS125A a National Semiconductor 54LS125A/DM54LS125A/OM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

ls125a

Contextual Info: LS125A National Semiconductor 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description that two outputs will attempt to take a common bus to oppo­ site logic levels, the disable time is shorter than the enable time of the outputs. This device contains four independent gates each of which